Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

n-type buried layer covered semi-superjunction lateral double-diffused metal oxide semiconductor field effect transistor

An oxide semiconductor, lateral double diffusion technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as reducing the lateral breakdown voltage of SJ-LDMOS devices, the P-type column region cannot be completely depleted, and the charge balance is broken. , to achieve the effect of low specific on-resistance, high breakdown voltage, and improving the contradictory relationship

Active Publication Date: 2018-03-02
华羿微电子股份有限公司 +1
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, for SJ-LDMOS, due to the substrate-assisted depletion of the N-type pillar region (or P-type pillar region), the P-type pillar region (or N-type pillar region) cannot be completely depleted when the device breaks down, breaking the N-type pillar region. The charge balance between the column area and the P-type column area reduces the lateral breakdown voltage of the SJ-LDMOS device
[0005] The semi-super junction, that is, the super junction region occupies half or part of the drift region. Compared with the ordinary super junction, an electric field peak is added to increase the breakdown voltage, but there is also the same substrate-assisted effect as the ordinary super junction. defect

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • n-type buried layer covered semi-superjunction lateral double-diffused metal oxide semiconductor field effect transistor
  • n-type buried layer covered semi-superjunction lateral double-diffused metal oxide semiconductor field effect transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0027] see figure 1 with figure 2 In the following, an N-type buried-layer-covered (N-channel) semi-superjunction lateral double-diffused metal-oxide-semiconductor field effect transistor is taken as an example to specifically introduce the new structure in the embodiment of the present invention. Those skilled in the art should be able to recognize that this embodiment does not limit the protection scope of the present invention.

[0028] The N-type buried layer covered semi-superjunction lateral double-diffused metal oxide semiconductor field effect transistor includes:

[0029] P-type substrate 1;

[0030] a P-type base region 2 located on the surface of the P-type epitaxial layer on the P-type substrate;

[0031] An N-type source region 7 located on a part of the surface of the P-type base region;

[0032] The semi-super junction region is arranged at intervals between the N-type pillar region 4 and the P-type pillar region 5 (two cycles are shown in the figure), and ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An N type buried layer cover type semi super junction transverse double diffusion metal oxide semiconductor field effect tube is disclosed. The invention discloses a novel SJ- LDMOS device. A semi super junction is manufactured on a P type epitaxial layer, and N type buried layers are introduced on a semi super junction area and some epitaxial films. Compared with a traditional SJ-LDMOS, according to the N type buried layer cover type semi super junction transverse double diffusion metal oxide semiconductor field effect tube of the invention, through the effect of the N type buried layers, the load imbalance between an N type column area and a P type column area in a super junction is compensated, a substrate assistant effect is overcome, breakdown voltage is raised, due to a semi super junction, an electric field peak is introduced at the surface, and the breakdown voltage is raised further. At the same time, a new conductive path is added outside the N type buried layers, and the specific on-resistance is reduced. The characteristic of the structure is the balance of high breakdown voltage, low conduction resistance and super junction layer load. The invention provides the novel SJ-LDMOS device has the characteristics of relatively simple fabrication process and low processing difficulty. The application requirement of a power electronic system is satisfied.

Description

technical field [0001] The invention relates to the technical field of semiconductor power devices, in particular to a semi-superjunction lateral double-diffused metal oxide semiconductor field effect transistor. Background technique [0002] The lateral power semiconductor device LDMOS (Lateral Double-diffused MOSFET) is characterized by a lateral channel, while the gate, source and drain are all on the same side of the chip, which is easy to integrate with low-voltage signals through internal connections. The advantages of frequency characteristics, gain, linearity, and switching performance have become the key to realizing the core technologies that lead to the second electronic revolution: PIC (Power Integrated Circuit) and HVIC (High Voltage Integrated Circuit). [0003] The super junction (super junction) structure is alternately arranged N-type pillar regions and P-type pillar regions. If the super junction structure is used to replace the drift region of LDMOS, a sup...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06
CPCH01L29/0615H01L29/7816
Inventor 段宝兴董超范玮杨银堂朱樟明马剑冲李春来
Owner 华羿微电子股份有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products