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P-type buried layer covered superjunction lateral double diffused metal oxide semiconductor field effect transistor

An oxide semiconductor, lateral double diffusion technology, applied in semiconductor devices, electrical components, circuits, etc., can solve the problems of reducing SJ-LDMOS breakdown voltage, low specific on-resistance, high breakdown voltage, etc.

Active Publication Date: 2017-08-29
XIDIAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The present invention proposes a P-type buried layer-covered superjunction lateral double-diffused metal oxide semiconductor field effect transistor to solve the problem that the substrate-assisted depletion effect reduces the breakdown voltage of SJ-LDMOS, and to improve the breakdown voltage and The contradictory relationship between the specific on-resistance achieves high breakdown voltage and low specific on-resistance

Method used

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  • P-type buried layer covered superjunction lateral double diffused metal oxide semiconductor field effect transistor
  • P-type buried layer covered superjunction lateral double diffused metal oxide semiconductor field effect transistor

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Embodiment Construction

[0028] see figure 1 and figure 2 In the following, a P-type buried layer-covered N-channel superjunction lateral double-diffused metal-oxide-semiconductor field-effect transistor is used as an example to specifically introduce the new structure in the embodiment of the present invention:

[0029] P-type buried layer covered N-channel super-junction lateral double-diffused metal oxide semiconductor field effect transistor, including:

[0030] P-type semiconductor substrate 1;

[0031] The P-type base region 2 and the N-type buffer layer 3 adjacent to the surface of the N-type epitaxial layer 9 on the P-type semiconductor substrate;

[0032] The super junction region adjacent to the P-type base region on the N-type buffer layer 3 includes N-type pillar regions 4 and P-type pillar regions 5 arranged laterally and periodically;

[0033] The P-type doped buried layer 8 located on the N-type pillar region 4 and only adjacent to the N-type drain region 6 has an N-type drift regio...

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Abstract

The invention discloses a new SJ-LDMOS device. Compared with a traditional SJ-LDMOS, by means of the combined action of a P-type buried layer and a buffer layer, charge imbalance between an N-type column region and a P-type column region in a super junction is compensated, the substrate-assisted effect is overcome, and breakdown voltage is increased; the P-type buried layer can increase the concentration of the N-type buffer layer, and therefore specific on-resistance is reduced. It is observed that the structure has the advantages of the high breakdown voltage, the low on-resistance and charge balance in a super-junction layer. The new SJ-LDMOS device structure has the advantages of being simple in manufacturing technology and low in technology difficulty and meets the application requirement of a power electronic system more easily.

Description

technical field [0001] The invention relates to the technical field of semiconductor power devices, in particular to a superjunction lateral double-diffused metal oxide semiconductor field effect transistor. Background technique [0002] The lateral high-voltage power semiconductor device LDMOS (Lateral Double-diffused MOSFET) refers to a high-voltage power MOS device with a lateral channel structure. Since the drain, source and gate of this type of device are all on the surface of the chip, it is easy to integrate with low-voltage signal circuits through internal connections, so it is the key to technology in high-voltage integrated circuits (HVIC) and power integrated circuits (PIC). But in power MOS device design, the on-resistance (R on ) As the breakdown voltage (BV) increases at a rate of 2.5 powers, the high-voltage application of power MOS is greatly restricted. [0003] The super junction (super junction) structure is alternately arranged N-type pillar regions and...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/36
Inventor 段宝兴李春来杨银堂马剑冲袁嵩
Owner XIDIAN UNIV
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