A Cache Replacement Method in Heterogeneous Memory Environment

Abstract

The invention discloses a cache replacement method in a heterogeneous memory environment, which is characterized in that it includes: adding a source flag bit in the cache line hardware structure to mark whether the cache line data comes from DRAM or PCM; A new sampling storage unit is added in the CPU, which is used to record program memory access behavior and data reuse distance information; it also includes three sub-methods: sampling method, equivalent position calculation method and replacement method. Sampling statistics, the equivalent location calculation submethod is used to calculate the equivalent location, and the replacement submethod is used to determine the cache line that needs to be replaced. The present invention optimizes the traditional cache replacement strategy for the memory access characteristics of programs in a heterogeneous memory environment. The implementation of the present invention can reduce the high delay cost of accessing PCM memory due to cache misses, thereby improving the overall memory access of the system performance.

Description

technical field [0001] The invention belongs to the technical field of computer science, and more specifically relates to a cache replacement method in a heterogeneous memory environment. Background technique [0002] The development of traditional memory technology represented by Dynamic Random Access Memory (DRAM) has encountered a bottleneck in recent years. Restricted by the manufacturing process, it is becoming more and more difficult to obtain larger capacity DRAM memory at a lower cost; and as the capacity continues to increase, the problem of high energy consumption of DRAM memory is becoming increasingly prominent. The rise and development of new non-volatile memory (Non-Volatile Memory, NVM for short) technology provides an opportunity to break the traditional DRAM memory, which is the bottleneck of system performance and energy consumption. Non-volatile memory devices represented by Phase Change Memory (PCM) have good scalability, and are closer to the delay and ...

AI Technical Summary

Problems solved by technology

The quality of the cache replacement algorithm directly affects the efficiency of the cache, which in turn can affect the overall performance of the system

The traditional cache replacement algorithm represented by LRU and its derivative algorithm has achieved good performance in the traditional DRAM memory environment, but in the heterogeneous memory environment, the cache miss penalty (Miss Penalty) is inconsistent, that is, the DRAM and PCM The new feature of inconsistent access latency has not been fully considered in the traditional cache replacement algorithm, which raises the problem of improving cache usage efficiency in a heterogeneous memory environment

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