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Clock pulse adjusting device and clock pulse adjusting method

A technology of adjustment device and adjustment method, applied in the direction of adjustment of electrical variables, control/regulation system, automatic power control, etc., can solve the problems of worst process conditions, inability to solve parameter adjustment, low working clock and operating voltage efficiency, etc. , to achieve smooth adjustment and avoid errors

Active Publication Date: 2015-08-12
ALI (CHENGDU) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This technology cannot solve the parameter adjustment under different process conditions, and can only consider the worst process conditions, resulting in low efficiency in adjusting the working clock and operating voltage

Method used

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  • Clock pulse adjusting device and clock pulse adjusting method
  • Clock pulse adjusting device and clock pulse adjusting method
  • Clock pulse adjusting device and clock pulse adjusting method

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Embodiment Construction

[0051] The current DVFS technology in integrated circuits can only consider the worst process conditions and cannot solve parameter adjustments under different process conditions, resulting in low efficiency in adjusting the working clock and operating voltage. The performance adjustment module of the clock adjustment device of the present invention can obtain a plurality of current performance codes for the current ambient temperature or operating conditions according to the time relationship and the space relationship, so as to determine whether the working clock and the operating voltage of the logic circuit need to be adjusted. In order to make the content of the present invention clearer, the following embodiments are specifically cited as examples on which the present invention can indeed be implemented. However, the scope of the present invention is not limited to the following examples.

[0052] figure 1 It is a block diagram of a clock adjustment device according to an e...

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PUM

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Abstract

The invention provides a clock pulse adjusting device and a clock pulse adjusting method. The clock pulse adjusting device comprises a first hardware performance monitor and a performance adjusting module. The first hardware performance monitor generates a plurality of current performance codes about propagation delay in dependence on operating conditions of a logical circuit at a time interval; each current performance code is correspondingly located at each time point at the time interval. The performance adjusting module is coupled to the first hardware performance monitor, receives the current performance codes, determines whether to adjust the work pulse of the logic circuit in dependence on the current performance codes, and adjusts an operation voltage in order to adapt for the work pulse. The performance adjusting module determines whether to increase the operation voltage in dependence on a worst value among the current performance codes, and determines whether to decrease the operation voltage in dependence on the average value of the current performance codes.

Description

Technical field [0001] The present invention relates to an adaptive adjustment technology of logic circuits, and more particularly to an adjustment device and method for dynamically adjusting operating voltage and / or operating clock. Background technique [0002] Dynamic Voltage and Frequency Scaling (DVFS) is to dynamically adjust the voltage and frequency to save the power consumption of the computer system or logic circuit. Due to the technological differences in the manufacturing processes of various integrated circuits and the influence of ambient temperature, the resulting integrated circuits will have a certain degree of drift in operating parameters. In the dynamic voltage and frequency adjustment of integrated circuits with different process conditions, the integrated circuit with the best process conditions does not need to adjust the operating voltage amplitude upwards, as the IC with the worst process conditions can meet the circuit timing requirements . [0003] Howe...

Claims

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Application Information

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IPC IPC(8): H03L7/08G05F1/46
Inventor 王世华
Owner ALI (CHENGDU) CORP
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