A Partial Reconfigurable Controller for Reconfigurable Systems

Abstract

The invention discloses a partial reconfiguration controller of a reconfigurable system. The partial reconfiguration controller comprises a plurality of reconfigurable computing array block controllers and block data flow diagram configuration information matched with the reconfigurable computing array block controllers. The whole reconfigurable system can be disassembled into a plurality of configurable array blocks and block control units. Each configurable array block comprises a plurality of computing array rows. Each block control unit comprises the corresponding computing array block controller. The computing array block controllers are responsible for analyzing the control flow configuration information of configurable computing array computing resources and controlling the data flow diagram execution processes of the rows in the configurable array blocks according to the time series configuration information. Different configurable computing array block controllers independently control data flow directions of the corresponding configurable array blocks. By means of the partial reconfiguration controller, multiple data flow control modes are supported, multi-data and multi-address interval inputting and multi-data and multi-address interval outputting are supported, the data reading-writing flexibility and the system configuration flexibility of the configurable system are guaranteed, and the performance of the configurable system is improved.

Description

technical field [0001] The invention relates to the technical field of embedded systems, in particular to a partial reconfiguration controller of a reconfigurable system. Background technique [0002] ASICs have high computing performance but poor flexibility, general-purpose processors have poor computing performance but high flexibility, and reconfigurable systems can change their functions through dynamic configuration while the system is running, while maintaining high computing performance, both high performance and Highly flexible computing advantages have been widely used in many fields. Facing the application requirements of increasingly complex computing tasks, the complexity of the controller structure and the capacity of configuration information required for reconfigurable systems to perform tasks are increasing, which affects the design of reconfigurable system chips and the computing performance of chips. In computing-intensive applications of large-scale reco...

AI Technical Summary

Problems solved by technology

In the computing-intensive applications of large-scale reconfigurable computing arrays, the configuration information of the reconfigurable system is relatively large, and the traditional system controller only relies on a single computing array controller to be responsible for the analysis of the reconfigurable computing array configuration information of the entire system And configuration, the burden on the controller is heavy, resulting in slow running speed and low efficiency of the reconfigurable system chip, and the controller generally only supports a single data flow control mode for reading and writing continuous address data, which is less flexible

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