A method for improving the real-time display speed of a-scan waveform of flaw detector

Abstract

The invention provides a method for improving the real-time display speed of the A-scan waveform of a flaw detector. In the hardware circuit adopted, the front-end circuit and the CPU are respectively connected to the FPGA, and the display screen of the ultrasonic flaw detector is connected to the FPGA; the functional modules implemented by the FPGA logic include A-scan Waveform forming module, video memory controller module, display controller module and overlay module; A-scan waveform forming module converts the sampling data sent by the front-end circuit into A-scan waveform and transmits it to the overlay module; CPU generates other image content on the display screen and It is transmitted to the overlay module through the video memory controller module; after the overlay module superimposes the image content from the A-scan waveform forming module and the video memory controller module, it is sent to the display screen for display through the display controller module. This method can improve the real-time response speed of the A-scan waveform display of the ultrasonic flaw detector, and meet the demand for real-time observation of the A-scan flaw detection waveform under the condition that the detection accuracy and display accuracy of the ultrasonic flaw detector are getting higher and higher.

Description

technical field [0001] The invention relates to an ultrasonic flaw detector, in particular to a method for increasing the real-time display speed of an A-scan waveform of the flaw detector. Background technique [0002] In order to meet the demand for higher and higher detection accuracy, the front-end of the ultrasonic flaw detector adopts higher and higher sampling accuracy and sampling rate. At the same time, the screen size needs to be larger and the resolution is higher to display higher-precision images. image. [0003] The existing real-time display realization scheme of A-scan waveform of ultrasonic flaw detector is realized by CPU (Central Processing Unit) to realize the drawing of A-scan waveform and send it to the display controller to directly output the signal sequence that meets the requirements of the display screen. refer to image 3 , the hardware circuit used includes a front-end circuit, FPGA and CPU, the front-end circuit, FPGA and CPU are connected in s...

AI Technical Summary

Problems solved by technology

Since the CPU needs to process more and more data, once the CPU cannot handle it, it has to reduce the detection repetition frequency or display frame rate, which may cause missed detection during detection; or although it can be processed, but due to The CPU needs to obtain the waveform data from the FPGA, and it needs to wait for the data to be cached and read it at one time, and the CPU may also need to cache the data during the process of processing the data. The increase in the amount of data leads to an increase in the cache time, which is difficult to achieve Real-time display of the waveform, which affects the effectiveness of the detection

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