Array substrate and manufacturing method, testing method, display panel and display device of array substrate
A technology of array substrates and test lines, applied in nonlinear optics, instruments, optics, etc., can solve problems such as the complexity of the test process, and achieve a simple and easy-to-achieve effect in the test process
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Embodiment 1
[0044] see figure 1 , is a schematic diagram of a partial structure of an array substrate provided in Embodiment 1 of the present invention. The array substrate includes: a substrate, a plurality of gate lines 210-250 formed on the substrate, and a plurality of input terminals for gate scanning signals are formed 310-350, wherein the first end of each gate line (in figure 1The left side of the middle substrate) one-to-one connection with a gate scan signal input end; also includes a gate line test line 400 formed at the right edge of the substrate and a test signal detection terminal 500 formed at the upper edge of the substrate, wherein the gate There is also an insulating layer (not shown in the figure) between the electrode test line 400 and the grid lines 210-250, the grid line test line 300 is connected to the test signal detection terminal 500, and is connected with each grid line the second end of figure 1 There is a vertical overlapping region at the right side of th...
Embodiment 2
[0059] see image 3 Different from the array substrate provided in Embodiment 1, the grid line test line 400 is in the form of a ring at the second end of each grid line, and the ring includes two vertical overlapping regions with the grid line.
[0060] The advantage of such arrangement is that the gridline test line 400 can be used to test multiple gridlines. Combine below Figure 4 and Figure 5 Describe the testing process,
[0061] see Figure 4 , when the grid line 230 and the grid line 240 need to be tested, firstly, in one of the two vertical overlapping areas of the grid line 230 and the grid line test line 400 ( Figure 4 The gate line 230 is short-circuited with the gate line test line 400 at the vertical overlap region near the left, and then the signal is detected at the test signal detection terminal 500 to complete the test of the gate line 230 .
[0062] see later Figure 5 , cut off the ring of the gate test line 400 at the periphery of the short-connect...
Embodiment 3
[0066] see Figure 6 , different from the array substrate provided in Embodiment 2, the first ends of the gate lines 210, 230, 250 in odd rows (the ends connected to the gate scanning signal input terminals 310, 310, 350) and the gate scanning signal input terminals 310, 310, 350 are located at the left edge of the substrate, and the second end is located at the right edge of the substrate; and the first ends of the grid lines 220, 240 of the even rows (connected to one end of the gate scan signal input terminals 310, 310, 350 ) and the gate scanning signal input terminals 310, 310, 350 are located at the right edge of the substrate, and the second terminal is located at the left edge of the substrate. And two grid line test lines 410 and 420 are formed on the base, wherein the grid line test line 410 is located at the left edge of the base, and the grid line test line 420 is located at the right edge of the base, correspondingly including two test signal detection terminals ...
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