Method for processing synchronous logic structures in gate-level netlist

Abstract

The invention discloses a method for processing synchronous logic structures in a gate-level netlist. The method comprises the steps that, firstly, all the structures, with two registers cascaded, in the gate-level netlist to be processed are found out by utilizing scripts to converge into an element list 1; secondly, all elements in the element list 1 are analyzed by utilizing the scripts according to the structural relationship of clock trees, and elements, with the two registers belonging to the same clock domain, in the element list 1 are found out and marshaled to form an element list 2; thirdly, all potential asynchronous paths PAP in the netlist are found out by utilizing the scripts on the basis of registers DEF 1 of each element in the element list 2, and marshaled to form an element list 3; fourthly, all elements in the element list 3 are analyzed by utilizing the scripts according to the structure relation of the clock tree, it is further guaranteed that the two registers of the PAP are not in the same clock domain, and the elements are marshaled to form a list 4; fifthly, the information of the list 4 is provided to a simulation tool to be matched with the netlist to carry out simulation. The processing time of the method is counted by second, time is saved, and the method is efficient.

Description

【Technical field】 [0001] The invention relates to a method for processing synchronous logic structures in a gate-level netlist. 【Background technique】 [0002] see figure 1 As shown, it is a synchronous logic structure: the register DEF1 and the register DEF2 are located in the same clock domain clk1, and the two are cascaded to form a synchronization unit, which is used to receive the output signal from another register DEF0 of a different clock domain clk0 or its generate a signal. [0003] A few basic concepts: [0004] Synchronization logic structure: register DEF0, register DEF1 and register DEF2 are jointly composed. [0005] Synchronization unit: composed of register DEF1 and register DEF2. [0006] Potential asynchronous path PAP (potential asynchronous path): composed of register DEF0 and register DEF1 of the synchronization unit. [0007] Simple constraint: A constraint that groups all registers into one clock domain that is synchronized. [0008] Functional ...

AI Technical Summary

Problems solved by technology

[0010] However, the existing technology takes a long time to complete the goal. In large-scale circuits, the cycle is often measured in months and consumes a lot of human resources.

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