A kind of preparation method of superjunction structure

Abstract

The invention provides a method for preparing a super junction structure, which belongs to the technical field of semiconductor manufacturing technology. The method includes the following steps: 1) preparing the first N-type epitaxial layer on the substrate; 2) adopting multiple high-energy ion implantation processes, implanting P-type impurities in the region where P-type columns need to be fabricated in the first N-type epitaxial layer, forming the first N-type epitaxial layer. Implantation region; 3) Forming a second N-type epitaxial layer on the first N-type epitaxial layer and the first implantation region; 4) Using multiple high-energy ion implantation processes, in the region where P-type columns need to be fabricated in the second N-type epitaxial layer Implanting P-type impurities to form a second implantation region; 5) repeating steps 3) and 4) of the "epitaxy-multiple high-energy ion implantation" process until the withstand voltage requirement of the super junction structure is met. The invention realizes the implantation of P and N strips by using multiple high-energy ion implantations with different energies and doses, and obtains a superjunction structure with smaller widths of P and N strips, which overcomes the P strips caused by high-temperature annealing push junctions in traditional epitaxial implantation Severe expansion.

Description

technical field [0001] The invention belongs to the technical field of semiconductor process manufacturing, and in particular relates to a preparation method of a super junction structure. Background technique [0002] Power semiconductor devices have been widely used in consumer electronics, computers and peripherals, network communications, electronic special equipment and instruments due to their characteristics of high input impedance, low loss, fast switching speed, no secondary breakdown, and wide safe working area. Instrumentation, automotive electronics, LED display and electronic lighting and many other aspects. Although the power handling capacity of power semiconductor devices has been greatly improved, in the high-voltage field, due to the problem of on-resistance, the conduction loss of power semiconductor devices increases rapidly with the increase of withstand voltage. In order to improve withstand voltage and reduce conduction loss, a series of new structure...

AI Technical Summary

Problems solved by technology

This method only needs one deep groove etching and one deep groove epitaxial growth to form the epitaxial layer and super junction thickness that meet the withstand voltage requirements. Compared with the multiple epitaxy method, the process is simpler and the cost is also reduced. It is easy to form voids, and the process of etching trenches with large aspect ratios is difficult. It is difficult to achieve through vertical angles, and the groove width is not easy to control. It is difficult to achieve thin P and N strips in actual production. Therefore, this method also Not suitable for the preparation of high-voltage super-junction structures

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