Preparation method of super junction structure

Abstract

The invention provides a preparation method of a super junction structure, and belongs to the technical field of semiconductor manufacturing processes. The method comprises the following steps of: 1, preparing a first N-type epitaxial layer on a substrate; 2, by adopting a multiple high energy ion injection process, injecting P-type impurities into an area, in which a P-type column needs to be manufactured, of the first N-type epitaxial layer so as to form a first injection area; 3, forming a second N-type epitaxial layer on the first N-type epitaxial layer and the first injection area; 4, by adopting the multiple high energy ion injection process, injecting P-type impurities into an area, in which a P-type column needs to be manufactured, of the second N-type epitaxial layer so as to form a second injection area; and 5, repeating the processes of "epitaxy-multiple high energy ion injection" in steps 3 and 4 until the voltage resistance requirements of the super junction structure can be met. According to the preparation method of the super junction structure, which is provided by the invention, the injection of P and N bars is realized to obtain the super junction structure with the narrower P and N bars by adopting the multiple high energy ion injection with different energy and doses, therefore the defect of severe transverse spread of the P bars, which is caused by high temperature annealing knot pushing, in the conventional epitaxial injection can be overcome.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor process manufacturing, and specifically relates to a method for preparing a super junction structure. Background technique [0002] Power semiconductor devices have been widely used in consumer electronics, computers and peripherals, network communications, electronic special equipment and instruments due to their high input impedance, low loss, fast switching speed, no secondary breakdown, and wide safe working area. Instrumentation, automotive electronics, LED display and electronic lighting, etc. Although the power processing capability of power semiconductor devices has been greatly improved, in the high voltage field, due to the problem of on-resistance, the conduction loss of power semiconductor devices increases rapidly with the increase in withstand voltage. In order to improve the withstand voltage and reduce the conduction loss, a series of new structures and new technologies have emer...

AI Technical Summary

Problems solved by technology

This method only needs one deep groove etching and one deep groove epitaxial growth to form the epitaxial layer and super junction thickness that meet the withstand voltage requirements. Compared with the multiple epitaxy method, the process is simpler and the cost is also reduced. It is easy to form voids, and the process of etching trenches with large aspect ratios is difficult. It is difficult to achieve through vertical angles, and the groove width is not easy to control. It is difficult to achieve thin P and N strips in actual production. Therefore, this method also Not suitable for the preparation of high-voltage super-junction structures

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