Time-interleaved pipeline-sar type adc circuit

Abstract

The invention provides a time-interleaved Pipeline-SAR ADC circuit. The time-interleaved Pipeline-SAR ADC circuit reduces the mismatch of the offset voltage between the two channels by sharing the comparator between the two channels; in addition, the hardware resources required by the circuit and the clock signal driving circuit are reduced by sharing the comparator , thereby reducing the power consumption and area of ​​the system.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a time-interleaved Pipeline-SAR ADC circuit. Background technique [0002] With the rapid development of integrated circuit technology, the degree of digitalization in the global high-tech field is continuously deepening. Nowadays, the electronic industry has formed a pattern with digital technology as the main body. The increasing digitization and integration of semiconductor technology has promoted the development of microcontrollers (MCU), digital signal processors (DSP), and micromechanical electronic systems (MEMS). The continuous development also pushes the analog-to-digital conversion technology towards high-precision and high-speed development. In recent years, due to the rapid development of digital signal processing technology and the continuous emergence of new theories and new algorithms, the performance of digital signal processing devices has been compr...

AI Technical Summary

Problems solved by technology

However, since the time-interleaved Pipeline-SAR ADC consists of two channels, the mismatch between the channels, including sampling time mismatch, offset voltage mismatch, and gain mismatch, will lead to system performance degradation

In order to avoid these problems, people usually use various complex correction circuits to correct these errors. These correction circuits usually require additional hardware resources and clock phases, thereby increasing system power consumption and reducing conversion rates.

[0006] In the process of realizing the present invention, the applicant found that in the above-mentioned time-interleaved Pipeline-SAR ADC circuit, the larger number of comparators and the clock control circuit lead to larger digital power consumption and hardware resources

At the same time, the correction method is used to deal with the mismatch of the offset voltage between the two channels, which increases the complexity and power consumption of the circuit.

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