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Gate structure and forming method thereof

A gate structure and gate technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of the decrease of the capacitive coupling rate of the gate structure, and achieve the effect of improving the capacitive coupling rate and increasing the coupling capacitance

Inactive Publication Date: 2015-11-25
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of this application is to provide a gate structure and its formation method to solve the problem of the decrease in the capacitive coupling rate of the gate structure in the prior art

Method used

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  • Gate structure and forming method thereof
  • Gate structure and forming method thereof
  • Gate structure and forming method thereof

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Embodiment Construction

[0040] It should be pointed out that the following detailed description is exemplary and intended to provide further explanation to the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0041] It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprising" and / or "comprising" are used in this specification, it indicates There are features, steps, operations, means, components and / or combinations thereof.

[0042] For the convenience of description, spatially relative terms may be used here...

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Abstract

The application provides a gate structure and a forming method thereof. The gate structure, according to the application, includes first and second gates sequentially stacked on a substrate. The first gate comprises a first plane portion and at least one first projection portion projecting from the first plane portion. The second gate is disposed on the surfaces of the first plane portion and the first projection portion. According to the application, as the first gate is provided with the first plane portion and the at least one first projection portion projecting from the first plane portion and the second gate is disposed on the surfaces of the first plane portion and the first projection portion, the side of the first projection portion is added into the coupling area of the first gate and the second gate, thus the coupling capacitance between the first gate and the second gate is enhanced, and the capacitance coupling rate of the gate structure is improved as compared with that in the prior art.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a gate structure and a method for forming the same. Background technique [0002] FLASH (flash memory) devices are generally divided into two types according to their structures: stacked gate devices and split gate devices. Stacked gate devices usually include stacked floating gates and control gates, wherein the floating gate is located between the control gate and the substrate and is in a floating state for storing data; the control gate is connected to the word line for controlling the floating gate . The floating gate and the substrate are isolated by a tunnel oxide layer, the floating gate and the control gate are isolated by a dielectric layer, and each flash memory unit is isolated by a shallow trench isolation structure (STI: shallow trench isolation) to achieve The purpose of reducing the size of the storage device is to effectively ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/283H01L29/423
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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