Method of improving performance of flash memory

A memory and flash technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of oxygen-nitrogen-oxygen layer erosion and performance degradation of flash memory

Inactive Publication Date: 2005-03-23
MACRONIX INT CO LTD
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] In the prior art of unit cell oxidation, no matter using dry oxidation method, wet oxidation method or dry rapid oxidation method, serious oxygen-nitrogen-oxygen layer erosion phenomenon will occur, thus causing the oxygen-nitrogen-oxygen layer to be damaged. The increase in the thickness of the double oxide layer will inevitably increase the operating voltage, resulting in a decrease in the performance of the flash memory

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method of improving performance of flash memory
  • Method of improving performance of flash memory
  • Method of improving performance of flash memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0029] Such as Figure 5Shown is a cross-sectional view of a typical flash memory cell. The memory cell usually includes a substrate 100 and a thin gate dielectric layer, such as a gate oxide layer 110 (usually used as a tunnel oxide layer) formed on the substrate. On the surface of 100 , two stacked gate structures 160 are located on the gate oxide layer 110 . Wherein, the gate oxide layer 110 may be formed of silicon monoxide. The stacked gate structure 160 also includes a first polysilicon layer 120 as a floating gate located on the gate oxide layer 110, and an interpoly dielectric layer 130 located on the first polysilicon layer 120, and finally, a second polysilicon layer The silicon layer 140 overlaps the inner polycrystalline dielectric layer 130 as a control gate.

[0030] Such as Figure 5 As shown, the stacked gate structure 160 is formed using conventional etching methods. However, a problem usually created by this step is the formation of polysilicon residue 15...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The method of improving performance of flash memory includes providing one substrate; forming one tunneling oxide layer on the substrate; forming on the tunneling oxide layer two grid structures, each of which includes the first polysilicon layer as floating grid, one inner polycrystal dielectric layer, such as O-N-O layer on the floating grid and the second polysilicon layer as control grid on the inner polycrystal dielectric layer, and oxidizing crystal cell with oxygen free radical with slight erosion on the O-N-O layer, about 6% increase of grid capacitance coupling ratio, increase of 5 times in operation speed and elimination of residual polysilicon.

Description

(1) Technical field [0001] The present invention relates to a method for fabricating flash memory, and more particularly to a method for promoting the performance of flash memory by utilizing an oxygen free radical (Oxygen free radical) cell oxidation step. (2) Background technology [0002] The non-volatile memory element includes a flash erasable programmable read only memory (EEPROM, electrical erasable programmable read only memory). figure 1 Shown is a cross-sectional view of a typical flash memory unit cell. The memory cell usually includes a substrate 10 and a thin gate dielectric layer, such as a gate oxide layer (gate oxide) 20 (usually used as a through Then an oxide layer (tunnel oxide) is formed on the surface of the substrate 10 , and two stacked gate structures 70 are located on the gate oxide layer 20 . Wherein, the gate oxide layer 20 may be formed of silicon monoxide. The stacked gate structure 70 includes a first polysilicon layer 30 as a floating gate on...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/82H01L21/8239
Inventor 韩宗廷苏俊联苏金达
Owner MACRONIX INT CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap