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Flash memory and method of forming the same

A memory and flash technology, applied in the field of flash memory and its formation, can solve the problems affecting the performance of flash memory, small capacitive coupling rate, and reduced facing area, so as to improve operation speed and efficiency, and improve capacitive coupling. rate, improve performance

Active Publication Date: 2018-07-10
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] However, with the continuous improvement of the integration level of integrated circuits and the continuous reduction of device dimensions, the size of the floating gate 3' has been reduced to below a micron, so that the control gate 6 and the floating gate 3' The reduction of the facing area leads to too small a capacitive coupling ratio, which seriously affects the performance of the flash memory

Method used

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  • Flash memory and method of forming the same
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  • Flash memory and method of forming the same

Examples

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Effect test

no. 1 example

[0043] This embodiment provides a method for forming a flash memory, including:

[0044] refer to Figure 5 , providing a substrate 110 on which a first dielectric material layer 120 is formed.

[0045] In a specific embodiment, the method of forming the first dielectric material layer 120 is chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0046] In a specific embodiment, the material of the first dielectric material layer 120 is a low-k material, such as one or more of amorphous carbon nitrogen, polycrystalline boron nitrogen, fluorosilicate glass, porous SiOCH and porous diamond. The upper surface of the substrate 110 may also be oxidized by a thermal oxidation method, and the formed oxide layer serves as the first dielectric material layer 120 .

[0047] In a specific embodiment, before forming the first dielectric material layer 120 , it further includes forming a source S and a drain D (not shown) in the substrate 110 .

[0048] The m...

no. 2 example

[0078] The difference between this embodiment and the first embodiment is:

[0079] refer to Figure 13 After depositing the floating gate material layer 130 on the tunnel dielectric layer 123, a patterned mask layer 104 is formed on the floating gate material layer 130, and the patterned mask layer 104 defines location of the floating gate.

[0080] Since the floating gate is to cover the upper surface and the sidewall of the protrusion 102, the patterned mask layer 104 must be located directly above the protrusion 102, and the patterned mask layer The width of 104 should be greater than the width of the protrusion 102 .

[0081] refer to Figure 14 , using the patterned mask layer 104 as a mask to etch the floating gate material layer 130 up to the upper surface of the tunnel dielectric layer 123 to form the floating gate 131 . After the floating gate 131 is formed, the patterned mask layer 104 is removed.

[0082] refer to Figure 15 , forming an inter-gate dielectric...

no. 3 example

[0091] The difference between the third embodiment and the first embodiment lies in that the method for forming the tunnel dielectric layer is different.

[0092] In the third embodiment, the method for forming the tunnel dielectric layer is:

[0093] refer to Figure 16 , forming a first dielectric material layer 120 on the substrate 110; forming a patterned mask layer 101 on the first dielectric material layer 120, and the patterned mask layer 101 defines the positions of the protrusions.

[0094] In a specific embodiment, the thickness of the first dielectric material layer 120 in this embodiment is equal to the sum of the thicknesses of the first dielectric material layer 120 and the second dielectric material layer 122 in the first embodiment.

[0095] For this step, reference may be made to the relevant steps in the first embodiment.

[0096] refer to Figure 17 , using the patterned mask layer 101 as a mask to etch a partial thickness of the first dielectric material...

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Abstract

A flash memory and its forming method, wherein the flash memory includes: a substrate; a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate sequentially arranged on the substrate from bottom to top; The tunnel dielectric layer includes a protrusion, and the floating gate covers the upper surface and the side wall of the protrusion. The flash memory provided by the invention has a high capacitive coupling rate.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a flash memory and a forming method thereof. Background technique [0002] Flash memory (Flash Cell) has the advantages of the stored data will not disappear after power failure, the access speed is fast, and the data can be stored, read, and erased multiple times, making it a popular choice for computers and electronic devices. A memory element that is widely used in devices and has become the most important non-volatile storage product at present. [0003] Flash memory generally has a stacked gate structure, including a tunnel dielectric layer, a floating gate (Floating Gate) for storing charges, an inter-gate dielectric layer, and a control gate (Control Gate) for controlling data access. In the prior art, methods for forming a flash memory include: [0004] refer to figure 1 , providing a substrate 1, on which a dielectric material layer 2 and a floating gate material layer 3...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11517H10B41/00H10B69/00
CPCH01L29/788H10B41/00
Inventor 孙光宇宋化龙
Owner SEMICON MFG INT (SHANGHAI) CORP
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