Semiconductor substrate, semiconductor package structure and manufacturing method thereof
A technology of packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components and other directions, and can solve problems such as increasing the thickness of the substrate
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[0022] see Figure 1A , FIG. 1 is a schematic diagram of a semiconductor substrate according to an embodiment of the present invention. Such as Figure 1A As shown, in one embodiment of the present invention, the semiconductor substrate 1a includes: a first patterned metal layer 13, a first dielectric layer 14, a second patterned metal layer 15, a conductive substance 15a, a second dielectric layer 16 and carrier layer 17 .
[0023] The first patterned metal layer 13 may include, but is not limited to, copper or other metals. The minimum line spacing and line width of the lines formed by the first patterned metal layer 13 may be 15 micrometers (μm). The first patterned metal layer 13 has a thickness from 5 microns to 20 microns.
[0024] The second patterned metal layer 15 is located below the first patterned metal layer 13 . The second patterned metal layer 15 may include, but is not limited to, copper or other metals. The second patterned metal layer 15 has a thickness f...
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