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Efficient time-interleaved analog-to-digital converter

A technology of analog-to-digital converter and time interleaving, which is applied in the direction of analog-to-digital converter, analog-to-digital conversion, code conversion, etc., and can solve problems such as trouble

Active Publication Date: 2015-12-09
FINGERPRINT CARDS ANACATUM IP AB
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

On the other hand, it can be cumbersome to design and verify that the constituent ADC designs operate at different clock frequencies

Method used

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  • Efficient time-interleaved analog-to-digital converter
  • Efficient time-interleaved analog-to-digital converter
  • Efficient time-interleaved analog-to-digital converter

Examples

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Embodiment Construction

[0061] In the following, an embodiment will be described in which a time-interleaved analog-to-digital converter (TIADC) has N processing paths, each processing path comprising a column of N component ADCs.

[0062] The constituent ADCs are clocked by an analog-to-digital converter operating clock signal (ADC clock), which typically has a fixed clock period associated with the design and hardware implementation of the constituent ADCs.

[0063] Other parts of the TIADC (eg, the sample-and-hold unit) are clocked based on a sample clock whose period is usually based on a flexible sample rate. Flexibility can be manifested in the implementation phase in that the number of processing paths is optimized for the sampling rate in question, and / or in use in that processing paths that become redundant for the current sampling rate can be Set to low energy mode.

[0064] Decoupling of the ADC clock from the sampling rate can cause the output samples from the constituent ADCs to be non-...

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Abstract

A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R is disclosed. The time-interleaved analog-to-digital converter comprises an array of an integer number N of constituent analog-to-digital converters, an integer number N of sample-and-hold units, one or more digital output processing units, and a timing circuit. Each constituent analog-to-digital converter is adapted to operate based on an analog-to-digital converter operation clock to provide a digital signal at the digital output. Each sample-and-hold unit is connected to the input of a respective constituent analog-to-digital converter and is adapted to operate based on a respective one of a number M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units. The digital output processing units are adapted to provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals. The timing circuit is adapted to generate the analog-to-digital converter operation clock signal and the M timing signals each timing signal having a period of M / R, wherein M is less or equal to N.

Description

technical field [0001] The present invention relates generally to the field of analog-to-digital converters, and more particularly, the present invention relates to the efficiency of time-interleaved analog-to-digital converters in terms of silicon area and / or energy. Background technique [0002] Electronic devices such as, for example, televisions and other audio / video devices are typically implemented using digital rather than analog technology. In general, the more advanced digital technology becomes, the more demanding the task of converting an analog signal into a digital signal suitable for digital technology implementation becomes. [0003] Conceptually, analog-to-digital converters (also called ADCs or A / D converters) and their basic functions (sample-and-hold, quantization) are well known in the art and will not be described in further detail herein. [0004] For high sampling frequencies it is necessary or at least beneficial to use an ADC structure comprising se...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12
CPCH03M1/126H03M1/1215H03M1/121H03M1/1255
Inventor 罗尔夫·松德布拉德埃米尔·亚尔马松
Owner FINGERPRINT CARDS ANACATUM IP AB