Efficient time-interleaved analog-to-digital converter
A technology of analog-to-digital converter and time interleaving, which is applied in the direction of analog-to-digital converter, analog-to-digital conversion, code conversion, etc., and can solve problems such as trouble
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[0061] In the following, an embodiment will be described in which a time-interleaved analog-to-digital converter (TIADC) has N processing paths, each processing path comprising a column of N component ADCs.
[0062] The constituent ADCs are clocked by an analog-to-digital converter operating clock signal (ADC clock), which typically has a fixed clock period associated with the design and hardware implementation of the constituent ADCs.
[0063] Other parts of the TIADC (eg, the sample-and-hold unit) are clocked based on a sample clock whose period is usually based on a flexible sample rate. Flexibility can be manifested in the implementation phase in that the number of processing paths is optimized for the sampling rate in question, and / or in use in that processing paths that become redundant for the current sampling rate can be Set to low energy mode.
[0064] Decoupling of the ADC clock from the sampling rate can cause the output samples from the constituent ADCs to be non-...
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