A Realization System of Product Correlation Algorithm Based on Adaptive Control Circuit

Abstract

The invention discloses a product correlation algorithm realization system based on an adaptive control circuit. Parallel split processing module, adder and output control circuit, algorithm function unit and adder are connected to output control circuit. In the present invention, as the size of the image changes, the control circuit can adaptively divide the image into multiple sub-parts suitable for calculation, use the algorithm function unit to calculate the multiplication and addition values ​​of each sub-part, and obtain the sum of the multiplication and accumulation items to be calculated. value, according to the number of algorithm functional units required to calculate an image matching, the corresponding number of parallel channels is correspondingly reduced until the minimum is one channel, making full use of FPGA internal resources to achieve maximum algorithm parallelism and improve coprocessor computing performance.

Description

technical field [0001] The invention belongs to the technical field of product correlation algorithms, and in particular relates to a product correlation algorithm realization system based on an adaptive control circuit. The adaptive control circuit is used to optimize and control the product correlation algorithm circuit to realize the self-adaptation of the product correlation algorithm to different image sizes. , to achieve the optimal algorithm efficiency and hardware resource usage. Background technique [0002] In many fields such as image processing, pattern recognition and information search, it is necessary to perform matching operations on images. Commonly used matching operations include absolute difference, mean square error, and product correlation, among which the product correlation algorithm has the advantages of high precision, strong adaptability, and good robustness, and has been widely used in many fields. In engineering practice, normalized product corr...

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Problems solved by technology

The shortcomings at this time are obvious. On the one hand, when the matching operation with a size smaller than 64 is actually performed, a large amount of storage resources and multiply-accumulate resources are wasted. image 3 It shows that when the size of the thumbnail is 32×32, the underutilized storage and computing resources inside the FPGA product correlation algorithm coprocessor, the actual resource utilization rate is less than 50%; on the other hand, when the size of the thumbnail exceeds 64, the original Some designs can no longer meet the calculation requirements and need to be redesigned

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