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A system and method for downloading FPGA programs based on PCI or PCIe bus

A program downloading and bus technology, which is applied in the field of FPGA program downloading system, can solve problems such as huge labor costs, installation environment that does not allow personnel to enter, and system reliability decline

Inactive Publication Date: 2017-12-08
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to solve the problem that the circuit board needs to be disassembled when the FPGA program is updated in the prior art, and then connect the download cable to the JTAG interface to download the program; when the system is more complicated, the disassembly of the circuit board will cause system reliability problems decline, the installation environment of the equipment may not allow personnel to enter, and when the number of products is relatively large, the labor cost caused by sending people to process the FPGA program of the equipment will be very huge, and the proposed one based on PCI or FPGA program download system and method for PCIe bus

Method used

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  • A system and method for downloading FPGA programs based on PCI or PCIe bus
  • A system and method for downloading FPGA programs based on PCI or PCIe bus
  • A system and method for downloading FPGA programs based on PCI or PCIe bus

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specific Embodiment approach 1

[0044] Specific embodiment one: a kind of FPGA program downloading system based on PCI / PCIe bus of the present embodiment comprises host computer, FPGA and EPCS configuration chip; The hardware structural block diagram of system is as follows figure 1 As shown in the figure, Altera's FPGA and EPCS Flash configuration chip are taken as examples to elaborate;

[0045] The host computer and the FPGA carry out data transmission through the PCI / PCIe bus; the host computer in this system is a computer; the FPGA includes a PCI / PCIe bus controller, an Avalon bus, an EPCS controller, and user-defined Development needs to be added by yourself, such as analog quantity acquisition function, switch quantity acquisition function, 1553B bus monitoring function, etc.);

[0046] The upper computer is connected to the PCI / PCIe bus controller through the PCI / PCIe bus, the PCI / PCIe bus controller is connected to the Avalon bus, the Avalon bus is connected to the user-defined functional components...

specific Embodiment approach 2

[0054] Specific implementation mode two: combination image 3 Describe this embodiment, a kind of FPGA program downloading method based on PCI / PCIe bus of this embodiment, specifically prepare according to the following steps:

[0055] Step 1. Start;

[0056] Step 2, using the fopen function of the C language to open the FPGA configuration file in the flash format to be downloaded and the NiosII project file in the flash format to be downloaded;

[0057] Step 3, convert the FPGA configuration file in flash format to be downloaded and the NiosII project file data in flash format to be downloaded into binary data and merge the two into a binary format file to obtain the merged binary format file;

[0058] Step 4, utilize the fread function of C language to read the binary format file after merging to computer memory;

[0059] Step 5, the host computer calls the alt_epcs_flash_write function in the Altera function library to control the EPCS controller in the FPGA to write the ...

specific Embodiment approach 3

[0069] Specific embodiment three: what this embodiment is different from specific embodiment two is: utilize the fopen function of C language in the described step 2 to open the FPGA configuration file of the flash format to be downloaded and the NiosII project file of the flash format to be downloaded; The process is:

[0070] In this design, because the program is to be downloaded to EPCS Flash, the selected program file to be downloaded must be a fixed file format suitable for the Flash device. This upper computer design uses the commonly used .flash format file, which can usually be developed using NiosII integration Tools in the software such as Flash Downloader (Flash Programmer) or command line window (ShellCommand) convert the FPGA configuration file in .sof format and the NiosII project file in .elf format to be downloaded into corresponding FPGA configuration files and NiosII project in flash format file, then utilize the fopen function of C language to open the FPGA...

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Abstract

The invention relates to an FPGA program downloading system based on a PCI or PCIe bus, and a method and solves problems that FPGA program downloading efficiency through a traditional JTAG mode is low, and system reliability deceases as a circuit board or external cables are dismounted during update of the FPGA program. The FPGA program downloading system based on the PCI / the PCIe bus comprises a host, an FPGA and an EPCS configuration chip, the host is connected with the FPGA through the PCI / the PCIe bus, the FPGA comprises a PCI / the PCIe bus controller, an Avalon bus, an EPCS controller and a function assembly customized by a user, inner assemblies of the FPGA are connected through the Avalon bus, and the EPCS configuration chip is connected with the FPGA. The FPGA program downloading system based on the PCI or PCIe bus is applied to the FPGA program downloading field.

Description

technical field [0001] The invention relates to an FPGA program downloading system and method based on PCI or PCIe bus. Background technique [0002] The traditional field programmable gate array (Field Programmable Gate Array, FPGA) device is widely used in electronics, communication, industrial control, etc. It has wide application in many fields. The architecture of mainstream FPGAs mainly includes two design modes: SRAM Base and Anti-fuse. Among them, SRAM Base is characterized by reprogrammable, low power consumption, and system reconfiguration; Repeat revisions. Most of the FPGAs currently on the market are based on the SRAM Base process. Since SRAM has the characteristic of losing data when it is powered off, the internal logic of the FPGA will also disappear when it is powered off. Therefore, in the design of FPGA products, it is generally necessary to use off-chip non-volatile memories such as EPROM and FLASH to store programs, and the FPGA reads configuration da...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/40
CPCG06F13/4068G06F2213/0024
Inventor 任广辉朱海辉江立辉张军齐何胜阳
Owner HARBIN INST OF TECH
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