A ldmos‑scr device with source-side embedded interdigitated nmos

Abstract

An LDMOS‑SCR device with source-side embedded interdigitated NMOS for improved ESD protection reliability of on-chip ICs. Mainly composed of P substrate, P epitaxy, P well, N well, first N+ implantation region, second N+ implantation region, first P+ implantation region, third N+ implantation region, fourth N+ implantation region, second P+ implantation region , the fifth N+ implantation region, a plurality of polysilicon gates, a plurality of thin gate oxide layers and a plurality of field oxygen isolation regions. On the one hand, the device forms a parasitic LDMOS-SCR current path by the second P+ injection region, the third polysilicon gate, the fifth N+ injection region, the N well, the P well, the first P+ injection region, and the first N+ injection region. The ESD robustness of the device can be enhanced; on the other hand, the first N+ implantation region, the first polysilicon gate, the first thin gate oxide layer, the second N+ implantation region, the first P+ implantation region, and the third N+ implantation region The interdigitated NMOS and parasitic resistance formed by the second polysilicon gate, the second thin gate oxide layer and the fourth N+ implantation region can form a resistance-capacitance coupling effect and increase the sustaining voltage.

Description

technical field [0001] The invention belongs to the field of electrostatic discharge protection of integrated circuits and relates to an ESD protection device, in particular to an ESD protection device with an LDMOS-SCR embedded with interdigitated NMOS at the source end, which can be used to improve the reliability of ESD protection of ICs on a chip . Background technique [0002] ESD (electrostatic discharge) is one of the important factors affecting the reliability of today's IC. Circuit dysfunction or gate oxide breakdown damage caused by ESD to ICs has attracted widespread attention in the industry. The damage phenomenon caused by ESD in IC is mainly manifested in the following aspects: dielectric breakdown caused by ESD in semiconductor devices, resulting in rupture of oxide film; local overheating of internal circuits caused by EOS (electrical overstress) or ESD in IC , leading to the melting of metal wires; in ESD protection devices, due to the low voltage clamping...

AI Technical Summary

Problems solved by technology

[0004] In view of the common problems of low maintenance voltage and insufficient anti-latch-up ability of the existing ESD protection devices with SCR structure, the present invention designs an LDMOS-SCR device with interdigitated NMOS embedded in the source end, which not only makes full use of the SCR The device is characterized by strong robustness, and the resistance-capacitance coupling effect formed by the increased N+ implantation region at the source of the device, the polysilicon gate and the thin gate oxide layer is used to improve the maintenance voltage of the ESD protection design scheme and enhance the ESD robustness of the device sex

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