Method for forming copper interconnect structure

Abstract

The invention discloses a copper interconnection structure forming method, and the method comprises the steps: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming a hole groove structure in the dielectric layer; forming copper manganese layers at the bottom of the hole groove structure and on side walls of the hole groove structure; and forming copper layers, filled in the hole groove structure, on the copper manganese layers. After the hole groove structure is formed in the dielectric layer, the copper manganese layers are formed at the bottom of the hole groove structure and on side walls of the hole groove structure, and then the copper layers, filled in the hole groove structure, are formed on the copper manganese layers, thereby preventing a gap from being formed in a copper interconnection structure, improving the quality of the copper interconnection structure, and reducing the forming technology difficulty of the copper interconnection structure.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a copper interconnection structure. Background technique [0002] With the development of semiconductor technology, the integration level of VLSI chips has reached hundreds of millions or even billions of devices, and multi-layer metal interconnection technology with more than two layers is widely used. Traditional metal interconnects are made of aluminum metal, but with the continuous reduction of device feature size in integrated circuit chips, the current density in metal interconnect lines continues to increase, and the required response time continues to decrease. Traditional aluminum Interconnect lines are no longer adequate. As process geometries shrink, copper interconnect technology has replaced aluminum interconnect technology. Compared with aluminum, metallic copper has a lower resistivity, and copper interconnects can reduce the resist...

AI Technical Summary

Problems solved by technology

With the continuous improvement of the technology level, the feature size (critical dimension, CD) of the device is continuously reduced, the width of the contact hole and the trench structure is continuously reduced, and its aspect ratio is getting larger and larger. In the contact hole or trench structure Internal defects are prone to occur: that is, as the electroplating process continues, the copper film is sealed in advance and is not completely filled, resulting in the formation of void defects in the contact hole or trench structure, thereby reducing the reliability of the device

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