Technology mapping method of multipath selector based on FPGA

Abstract

The invention relates to a technology mapping method of a multipath selector based on FPGA. The method is used for realizing a six-for-one selector in an LP, wherein the LP comprises two LUT4 and one LUT4C. The method comprises steps that, a third input signal and a fourth input signal are outputted through a first gating signal and a second gating signal in combination with the gating LUT4C, or a first input signal or a second input signal outputted by an output end of the first LUT4 connected with an LUT4C input end is outputted; gating of the second LUT4 is realized through the second gating signal to output a fifth input signal or a sixth input signal; the LUT4C and an output end of the second LUT4 are respectively connected with two input ends of a two-for-one selector; according to a third gating signal, gating of the two-for-one selector is realized to output the first input signal, or the second input signal, or the third input signal, or the fourth input signal, or the fifth input signal or the sixth input signal.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a method for process mapping of FPGA-based multiplexers. Background technique [0002] Field-Programmable Gate Array (Field-Programmable GateArray, FPGA) is a logic device with abundant hardware resources, powerful parallel processing capability and flexible reconfigurable capability. These features make FPGA more and more widely used in data processing, communication, network and many other fields. [0003] In FPGA application design, multiplexer (MUX) is a widely used general-purpose device. In the traditional process mapping method, the schematic diagram of the logic mapping of the six-choice selector based on the four-input look-up table (LUT4) can be as follows figure 1 shown. The first LUT4 gates the input signals i0 and i1, the second LUT4 gates the input signals i2 and i3, and the third LUT4 gates the input signals i4 and i5; The signal is connected to the...

AI Technical Summary

Problems solved by technology

According to the process mapping method of the above six selectors, the logic needs 4 LUT4s to be realized. Therefore, based on the CMEM5 or CMEM7 architecture, the logic mapping using the above process mapping method needs to occupy at least two LP resources to be realized.

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