Dual-mode switching LDO circuit

Abstract

The invention discloses a dual-mode switching type LDO circuit which comprises a first LDO main circuit, a second LDO main circuit and a dynamic load circuit. The dynamic load circuit comprises a current comparator and a current discharge path. Image current of tail current across the second main circuit and image current across a first active load are compared through the current comparator, and the current discharge path connected between the output end of the second main circuit and the ground is controlled to be switched on and off according to the comparison result. In the process of switching a large driving mode to a low power consumption mode, the current discharge path can be controlled by a feedback loop to be switched on, and therefore the influence of electric leakage of a drain electrode of a first PMOS transistor of the first main circuit can be eliminated, and LDO output voltage is kept stable.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing, in particular to a dual-mode switching low-dropout linear regulator (LDO) circuit. Background technique [0002] In the design of ultra-low power MCU, LDO is an essential module, and LDO should provide a stable core (core) voltage. Such as figure 1 As shown, it is a dual-mode switching LDO circuit; the existing dual-mode switching LDO circuit includes: a first LDO main circuit 1 and a second LDO main circuit 2 . [0003] The driving current of the first LDO main circuit 1 is greater than the driving current of the second LDO main circuit 2, and the first LDO main circuit 1 is used to provide an LDO output voltage VPWR in a large driving mode (Active Mode); The power consumption of the second LDO main circuit 2 is less than the power consumption of the first LDO main circuit 1, and the second LDO main circuit 2 is used to provide the LDO output voltage VPWR in the low power con...

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Problems solved by technology

[0009] However, in the Active LDO, due to the need to provide a large driving capability, the size of the first PMOS transistor Ppass0 will be large. When switching to the Standby state (sw1 is closed, sw2 is open, sw0 is closed), the first PMOS transistor Ppass0 will have leakage current. Especially at high temperature, the leakage current will flow through the resistors R3 and R4, affecting the feedback loop of the Standby LDO, thus charging the output VPWR of the LDO high

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