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Semiconductor package and manufacturing method thereof

A package and semiconductor technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of increased production costs, inability to place, and difficulty in increasing production, so as to increase production and save cost reduction effect

Active Publication Date: 2019-01-04
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] However, in the current manufacturing method of semiconductor package 1, the current cutting machine can only place a maximum of 100mm×240mm, so it cannot place a size of 370mm×470mm or larger. Therefore, at this stage, manual cut into a suitable size, and then put it into the existing single cutting machine, making it difficult to increase the output
[0013] In addition, if the layout of 370㎜×470㎜ or larger is to be directly cut to order, an additional special machine is required, resulting in an increase in product production costs.

Method used

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  • Semiconductor package and manufacturing method thereof
  • Semiconductor package and manufacturing method thereof
  • Semiconductor package and manufacturing method thereof

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Embodiment Construction

[0042] The implementation of the present invention will be described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0043] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for the understanding and reading of those skilled in the art, and are not used to limit the implementation of the present invention. Limiting conditions, so it has no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size should still fall within the scope of the present invention without affecting the effect and purpose of the present invention. The disclosed technical content must be within the scope covered. At the same time, the terms such as "above" and "a" quoted ...

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Abstract

The invention discloses a semiconductor packaging part and a manufacturing method therefor. The method comprises the steps: firstly providing a bearing part with a plurality of grooves, and a plurality of carriers, wherein each carrier is provided with a plurality of electronic elements; enabling all carriers to be correspondingly placed in the grooves, and enabling all electronic elements to be higher than the bearing part; forming a packaging material on the bearing part, so as to cover the electronic elements; removing all carriers and the bearing part; and finally carrying out separation. Through the design of the carriers and the grooves, the whole layout structure is divided into packaging blocks in a needed size, and later, a conventional machine platform can be used for cutting, thereby saving the development cost of the machine platform.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor package, in particular to a semiconductor package with increased production capacity and a method for manufacturing the same. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. In order to meet the packaging requirements of miniaturization of semiconductor packages, a wafer level packaging (Wafer Level Packaging, WLP) technology has been developed. [0003] like Figure 1A to Figure 1E , which is a schematic cross-sectional view of a conventional wafer-level semiconductor package 1 manufacturing method. [0004] like Figure 1A As shown, a thermal release tape 11 is formed on a carrier 10 . [0005] Next, place a plurality of semiconductor elements 12 on the thermal release adhesive layer 11, these semiconductor elements 12 have opposite active surf...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L21/56
CPCH01L21/568H01L2224/04105H01L2224/12105H01L2224/19H01L2224/73267
Inventor 陈彦亨林畯棠詹慕萱纪杰元
Owner SILICONWARE PRECISION IND CO LTD