Asymmetrical partition mode based high efficiency video coding adder tree parallel realization method

A high-efficiency video coding and dividing mode technology, which is applied in the field of integer pixel motion estimation in high-efficiency video coding, can solve problems such as increasing hardware area, and achieve the effect of speeding up computing speed, improving computing efficiency, and improving computing efficiency.

Active Publication Date: 2016-05-11
XIAN UNIV OF POSTS & TELECOMM
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Problems solved by technology

For HEVC, the maximum coding block size is 64×64 pixels. If the same or similar design architecture is used, 4096 computing units are required. Only in the part of SAD computing, its area is 16 times that of the H.264 architecture , so that the hardware area is greatly increased

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  • Asymmetrical partition mode based high efficiency video coding adder tree parallel realization method
  • Asymmetrical partition mode based high efficiency video coding adder tree parallel realization method
  • Asymmetrical partition mode based high efficiency video coding adder tree parallel realization method

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Embodiment Construction

[0048] The principles and features of the present invention are described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

[0049] The following embodiments provide a new and efficient implementation method of an additive tree including an asymmetric partition mode based on a two-dimensional array processing element,

[0050] figure 1 is a schematic diagram of PE adjacency interconnection, and the addition tree is implemented on the two-dimensional adjacency interconnection PE array;

[0051] figure 2 It is a schematic diagram of the addition tree array and the buffer area distribution, the gray part is the buffer area module (the leftmost column is the buffer area 1, the rightmost column is the buffer area 2, and the bottom row is the buffer area 3), and the 16×16 PEs in the middle are the addition The tree module uses a total of 18...

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Abstract

The invention discloses an asymmetrical partition mode based high efficiency video coding adder tree parallel realization method, relating to the technical field of digital video coding and decoding. According to the method, a two-dimension processing element array structure is adopted, and an SAD value of a brightness block partition mode is calculated and processed parallelly, so that the motion estimation operation efficiency is improved effectively. A PE for storing the SAD value is selected according to whether the SAD value is used in subsequent process, so that the calculation speed of anadder tree is improved, and the calculation efficiency is improved. In the conventional pixel block storage manner, a single PE stores a single pixel, while in the method, a single PE stores 4*4 pixel blocks, so that the quantity of processing units is reduced to 1 / 16 that of processing units in prior art. Compared with the adder tree serial structure realization method, the parallel structure improves the speed by nearly 92 times. Calculation of the SAD values of 36 partition modes is realized through merging of SAD values of 4*4 partition mode, so that excessive calculation steps are reduced, and the calculation efficiency is improved.

Description

technical field [0001] The present invention relates to the technical field of digital video coding and decoding, in particular to an integer pixel motion estimation method in High Efficiency Video Coding (HEVC for short). Background technique [0002] Motion estimation is a widely used technique in video coding and video processing. The basic idea of ​​motion estimation is that each frame in the graphics can be divided into non-overlapping blocks because there is a certain correlation between the scenes in the adjacent frames of the active image, and the displacement of all pixels in the block is considered to be the same. Then try to find out the position of each block in the adjacent frame, and get the relative offset of the two in the space position, the relative offset is usually called the motion vector, the process of obtaining the motion vector is called for motion estimation. [0003] With the continuous improvement of video quality, H.264 can no longer meet the c...

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Application Information

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IPC IPC(8): H04N19/176H04N19/105H04N19/119H04N19/137H04N19/436H04N19/51
CPCH04N19/105H04N19/119H04N19/137H04N19/176H04N19/436H04N19/51
Inventor 谢晓燕崔继兴蒋林吴进芦守鹏
Owner XIAN UNIV OF POSTS & TELECOMM
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