Three-dimensional laminated semiconductor structure and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor device, semiconductor/solid-state device components, etc., can solve problems such as inability to meet, poor SSL island profile, poor word line connection, etc.
Active Publication Date: 2016-05-18
MACRONIX INT CO LTD
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Problems solved by technology
Since the traditional manufacturing method has carried out two etching processes (PLC process + PLA process), the problem of poor word line connection may occur in the fabricated structure
In the traditional manufacturing method, the non-self-aligned SSL cut is used to form the SSL island, so the SSL island may have a bad profile
Furthermore, in the traditional manufacturing method, the upper part 19b and the lower part 19a of the conductor 19 are made of the same material, which cannot meet the needs of word lines (upper part 19b) and gates (lower part 19a) with different characteristics.
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Embodiment Construction
[0057]The present invention proposes a three-dimensional stacked semiconductor structure and its manufacturing method. The three-dimensional stacked semiconductor structure of the embodiment can be fabricated by a word line damascene process (damascene WL process), which uses a self-aligned process to form word lines. According to the disclosed embodiments, the gate and the word line can be formed of different materials, so that the gate material has a proper work function (eg, high work function), while the word line material has a low resistance. Furthermore, the self-aligned double gate serial selection line process (self-aligned double gate SSL process) can be performed by bit line isolation (BLisolation). Accordingly, the three-dimensional stacked semiconductor structure of the embodiment has advantages such as self-aligned configuration of related elements, low resistance of word lines, and stable electronic characteristics. Furthermore, the three-dimensional stacked se...
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The invention discloses a three-dimensional laminated semiconductor structure and a manufacturing method thereof. The three-dimensional laminated semiconductor structure comprises multiple multi-layered pillars, multiple first conductors, multiple charging-trapping layers and a second conductor, wherein the multiple multi-layered pillars are formed on a substrate at intervals; the multiple first conductors are formed between adjacent multi-layered pillars; the multiple charging-trapping layers are formed on the substrate and the side walls of the multi-layered pillars to separate the first conductors and the multi-layered pillars; and the second conductor is formed on the first conductors and the charging-trapping layers. In the embodiment of the invention, one of the multi-layered pillars is formed by multi-layered insulated layers and multi-layered conductive layers in an alternate laminated mode. The upper surface of each first conductor is higher than that of each multi-layered pillar to enable an accommodating groove to be formed above the multi-layered pillar. In addition, the second conductor fills the accommodating grooves above the multi-layered pillar.
Description
technical field [0001] The present invention relates to a three-dimensional stacked semiconductor structure and its manufacturing method, and in particular to a three-dimensional stacked semiconductor structure made by a self-aligned process and its manufacturing method. Background technique [0002] A great feature of non-volatile memory element design is the ability to preserve the integrity of the data state when the memory element loses or removes power. Currently, many different types of non-volatile memory devices have been proposed in the industry. However, related companies are still developing new designs or combining existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND gate (NAND) flash memory structures have been proposed. However, there are still some problems to be solved in the current 3D stacked memory structure. [0003] Figure 1A ~ Figure 1C A conven...
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IPC IPC(8): H01L27/115H01L21/8247H01L21/768H01L23/532H10B43/35H10B43/20
Inventor 赖二琨
Owner MACRONIX INT CO LTD