Chip surface contact pressure calculation method and variable-scale manufacturability design method

Abstract

The invention discloses a chip surface contact pressure calculation method and a variable-scale manufacturability design method. The calculation method comprises the steps of performing grid division on a wafer surface where a chip is to obtain a plurality of first grids; calculating a contact pressure of each first grid by utilizing a contact mechanical equation set to obtain contact pressure distribution of the wafer surface, and marking the contact pressure distribution as first contact pressure distribution; dividing each first grid into a plurality of second grids; calculating a contact pressure of each second grid by utilizing the contact mechanical equation set to obtain contact pressure distribution in each first grid, and marking the contact pressure distribution as second contact pressure distribution; and according to the line width in each second grid, calculating contact pressure distribution in each second grid, marking the contact pressure distribution as third contact pressure distribution, and obtaining contact pressure distribution of the chip surface. According to the chip surface contact pressure calculation method provided by the invention, the calculation efficiency and the calculation precision can be considered simultaneously, thereby providing premise and guarantee for manufacturability design optimization.

Description

technical field [0001] The invention relates to the field of manufacturability design of integrated circuits, in particular to a method for calculating chip surface contact pressure and a method for manufacturability design with variable scale. Background technique [0002] In recent years, with the continuous expansion of integrated circuit wafer size and the continuous reduction of chip feature size, chip stability control has become increasingly difficult. Many derivative effects have not been fully considered before design, and the improvement of integrated circuit yield has been significantly affected. Therefore, the IC chip design process solution based on Design for Manufacturability (DFM) has become a frontier research hotspot in recent years. Design for Manufacturability (DFM), as a nascent nano-design methodology technology, provides a technical platform covering design and manufacturing information, so that designers can predict the impact of different design sche...

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Problems solved by technology

[0004] However, in the prior art, the CMP model and implementation technology that can take into account both the grinding mechanism and the calculation efficiency of the contact pressure between the polishing pad and the chip surface are very scarce, res...

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