Method for simplifying verification model implementation in chip verification

Abstract

The invention discloses a method for simplifying verification model implementation in chip verification. According to the method, an excitation generator, a verification model and a design model to be tested are included, the excitation generator is used for generating start signals and corresponding control signals required by a whole message and a processed message, the start signals and the corresponding control signals required by the whole message and the processed message exist in two queues in the excitation generator at the same time, and one of the queues is used for being sent to the design model to be tested; the verification model directly takes data and the control signals from the other queue in the excitation generator, obtains all the control signals required by the whole message and the processed message, can directly process the message data according to the designed requirement, stores the processed data according to the output interface behavior of the designed module to be tested and waits to compare the stored data with the result of design to be tested. By means of the method, implementation of the verification model is simplified, and a great quantity of chip verification time is saved.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a method for realizing a simplified verification model in chip verification. Background technique [0002] In the current chip verification, the stimulus generator and verification model are basically built according to the traditional verification architecture, such as figure 1 shown. The incentive generator is responsible for generating various incentives. At a certain moment, a message and the control signal required for processing the message are pre-generated and stored in a queue. According to the timing characteristics of the input interface of the design to be tested, these message data and control signals are divided into different fragments, sent out in chronological order, and sent to the excitation waveform that meets the requirements of the design to be tested. As the software implementation of the design under test, the verification model must be consistent...

AI Technical Summary

Problems solved by technology

[0003] The verification environment of this traditional architecture is relatively simple, but the disadvantages are also obvious: this will lead to complex implementation of the verification model, and a lot of energy will be spent on interface design, and the focus of our verification is the function and behavior of the design to be tested, not the verification model itself. interface design

In this way, when the verification model itself has problems, it will increase the difficulty of its own error detection, and increase the difficulty and time overhead of the verification model implementation, which is very unfavorable to the progress of chip verification.

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