Accuracy-Guaranteed Network Delay Calculation Method Based on Random Walk Capacitance Extraction

Abstract

The invention discloses a net time delay calculating method based on random walking capacitance extraction and ensuring accuracy; the method comprises the following steps: calculating the relationship between interconnection time delay random error and capacitance random error of a single input-single output interconnection line net or a single input-multi output interconnection line net; carrying out random walking capacitance extraction according to user assigned random walking capacitance extraction precision; building a RC equivalent circuit according to the extracted random walking capacitance value, and calculating interconnection time delay random error (i) according to the relationship between interconnection time delay random error and capacitance random error of the interconnection line net; if (i) does not satisfy user preset interconnection time delay random error threshold requirements, re-executing extraction process and following time delay calculation according to the set random walking capacitance extraction precision, and doing a plurality of iterations until the user preset interconnection time delay random error threshold requirements are satisfied. The novel method can ensure time delay error to be controlled, and the total calculation time including capacitance extraction can be minimized.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a method for calculating line network time delay with guaranteed accuracy based on random walk capacitance extraction. Background technique [0002] With the development of integrated circuit manufacturing technology, its feature size is gradually reduced and its integration degree is gradually increased. In the nano-scale manufacturing process (feature size below 65 nanometers) that has been widely used at present, the number of transistors integrated in a single chip has reached one billion. The resulting problem is that the interconnection delay accounts for an increasing proportion of the circuit delay. Therefore, in the physical design and verification of integrated circuits, accurate and fast extraction of parasitic parameters (calculation of parasitic resistance and capacitance of interconnection lines) and accurate analysis of interconnection delays have beco...

AI Technical Summary

Problems solved by technology

Although the calculation speed of the pattern matching method is fast, it often cannot meet the requirements of the nanoscale process due to the increase in the complexity of the interconnect structure and the accuracy of the design.

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