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DRAM-based reconfigurable device

A look-up table and storage array technology, applied in the field of reconfigurable processing units, which can solve problems such as undefined PLDs

Active Publication Date: 2020-10-09
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unlike logic gates or logic circuits, which usually have fixed functions, traditional PLDs have undefined functions at the time of manufacture

Method used

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  • DRAM-based reconfigurable device
  • DRAM-based reconfigurable device
  • DRAM-based reconfigurable device

Examples

Experimental program
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Embodiment Construction

[0022] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings in which some example embodiments are shown. The presently disclosed subject matter may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the presently disclosed subject matter to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.

[0023] It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer , connected or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as bei...

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Abstract

A DRAM-based reconfigurable logic. According to one general aspect, an apparatus may include a memory array including a plurality of memory sub-arrays. At least one of the sub-arrays may be arranged as a reconfigurable look-up table. The reconfigurable look-up table may include: a plurality of memory cells configured to store data; a local row decoder configured to activate a row or rows of memory cells based on a set of input signals; a local line selector , configured to select a subset of rows of memory cells based on at least one input signal.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application Serial No. 62 / 092,819, filed December 16, 2014, and entitled "DRAM-BASED RECONFIGURABLE LOGIC." The subject matter of this earlier filed application is incorporated herein by reference. [0003] This application claims priority to US Provisional Patent Application Serial No. 62 / 092,822, filed December 16, 2014, and entitled "HBM WITH DRAM-BASEDRECONFIGURABLE LOGIC ARCHITECTURE." The subject matter of this earlier filed application is incorporated herein by reference. [0004] This application claims priority to US Provisional Patent Application Serial No. 62 / 092,825, filed December 16, 2014, and entitled "SPACE-MULTIPLEXINGDRAM-BASEDRECONFIGURABLE LOGIC." The subject matter of this earlier filed application is incorporated herein by reference. technical field [0005] This specification relates to computing technology, and more particularly to recon...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/17736H03K19/17758H03K19/1776H03K19/17728H01L25/00H01L25/18
CPCH03K19/1776H03K19/17758H01L2924/0002H03K19/17728H03K19/17736H01L2924/00H01L25/18H01L25/50
Inventor 高鸣宇郑宏忠K.T.马拉迪
Owner SAMSUNG ELECTRONICS CO LTD