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Shifting register unit, grid driving circuit and display device

A shift register and gate technology, which is applied in the field of gate drive circuits, display devices, and shift register units, can solve the complex structure of shift register units, the different cascade relationships of shift register units, and the difficulty in application of display devices. big problem

Active Publication Date: 2016-07-06
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, although the adjustment of the scan duration can be realized by changing the structure of the shift register unit, this makes the structure of the shift register unit more complicated and the cascading relationship of the shift register units in the gate drive circuit is also different, resulting in the current It is more difficult to apply some gate drive circuits to display devices that need to adjust the scanning time of the gate lines according to the actual situation, and the production cost increases

Method used

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  • Shifting register unit, grid driving circuit and display device
  • Shifting register unit, grid driving circuit and display device
  • Shifting register unit, grid driving circuit and display device

Examples

Experimental program
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Effect test

Embodiment 1

[0101] by Figure 2a The structure of the shift register unit shown is taken as an example to describe its working process, wherein, in Figure 2a In the shift register unit shown, the potential of the first reference signal terminal VSS is low potential, and the potential of the second reference signal terminal VDD is high potential; the corresponding input and output timing diagram is as follows Figure 3a Shown, specifically, select as Figure 3a There are five stages T1, T2, T3, T4, and T5 in the shown input and output timing diagram, and the T2 stage is further divided into two stages, T21 and T22.

[0102] In the T1 stage, Input=0, CK1=0, CK2=1.

[0103] Since CK2=1, the third switch transistor M3 is turned off; because Input=0, the second switch transistor M2 is turned on; because the second switch transistor M2 is turned on and provides the high potential signal of the second clock signal terminal CK2 to The second node B, so the potential of the second node B is a ...

Embodiment 2

[0128] by Figure 2a The structure of the shift register unit shown is taken as an example to describe its working process, wherein, in Figure 2a In the shift register unit shown, the potential of the first reference signal terminal VSS is low potential, and the potential of the second reference signal terminal VDD is high potential; the corresponding input and output timing diagram is as follows Figure 3b Shown, specifically, select as Figure 3b There are five stages T1, T2, T3, T4 and T5 in the shown input and output timing diagram, and the T2 stage is further divided into four stages T21, T22, T23 and T24.

[0129] In the T1 stage, Input=0, CK1=0, CK2=1. The specific working process is the same as the working process of the T1 stage in the first embodiment, and will not be repeated here.

[0130] In the T2 stage, wherein, in the former time period of the T21 stage, Input=1, CK1=1, CK2=1; in the middle time period, Input=1, CK1=1, CK2=0; in the later time period, Input...

Embodiment 3

[0145] by Figure 2a The structure of the shift register unit shown is taken as an example to describe its working process, wherein, in Figure 2a In the shift register unit shown, the potential of the first reference signal terminal VSS is low potential, and the potential of the second reference signal terminal VDD is high potential; the corresponding input and output timing diagram is as follows Figure 3c Shown, specifically, select as Figure 3c There are five stages T1, T2, T3, T4 and T5 in the input and output timing diagram shown, and the T2 stage is further divided into six stages T21, T22, T23, T24, T25 and T26.

[0146] In the T1 stage, Input=0, CK1=0, CK2=1. The specific working process is the same as the working process of the T1 stage in the first embodiment, and will not be repeated here.

[0147] In the T2 stage, wherein, in the former time period of the T21 stage, Input=1, CK1=1, CK2=1; in the middle time period, Input=1, CK1=1, CK2=0; in the later time peri...

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Abstract

The invention discloses a shifting register unit, a grid driving circuit and a display device. The shifting register unit comprises an input module, a first control module, a second control module, a third control module, a first output module and a second output module. The above six modules are cooperated with each other, and by adjusting the duration of an effective pulse signal of an input signal end, the duration of a scanning signal output by a driving signal output end can be controlled. The electric potential of the driving signal output end is controlled by a first reference signal end and a second reference signal end, so that the stability of the driving signal output end can be improved. Compared with the prior art that the duration of the scanning signal output by the driving signal output end is controlled through the grid driving circuit of a complex structure, the difficulty of the grid driving circuit is lowered, and the process complexity is lowered, so that the cost is lowered.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register unit, a gate drive circuit and a display device. Background technique [0002] With the rapid development of display technology, the display panel is more and more developed towards the direction of high integration and low cost. Among them, the array shift register unit line drive (GateDriveronArray, GOA) technology integrates the thin film transistor (ThinFilmTransistor, TFT) gate switch circuit on the array shift register unit of the display panel to form a scan drive for the display panel, thus saving Removing the wiring space of the Bonding area of ​​the integrated circuit (Integrated Circuit, IC) and the fan-out (Fan-out) area can not only reduce the product cost in terms of material cost and manufacturing process, but also make the display panel Aesthetic design with symmetry on both sides and narrow borders; moreover, this integrated process can also sa...

Claims

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Application Information

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IPC IPC(8): G09G3/20G09G3/3266G09G3/36G11C19/28
CPCG09G3/20G09G3/3266G09G3/3674G11C19/28
Inventor 马占洁
Owner BOE TECH GRP CO LTD
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