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Check node operation unit, check node, storage device and information processing method

A technology of check nodes and computing units, applied in the information field, can solve problems such as reduction of storage resources and logic resources, sensitive data width, etc.

Inactive Publication Date: 2016-08-10
BEIJING LENOVO CORE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the storage resources of the decoder and the logic resources of each operation unit are sensitive to the data width, especially for the CNU unit where the key path is located and the EXCHANGE_RAM that stores all side information, the data transmitted between modules is reduced every time One bit, the storage resources and logic resources they occupy will be greatly reduced

Method used

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  • Check node operation unit, check node, storage device and information processing method
  • Check node operation unit, check node, storage device and information processing method
  • Check node operation unit, check node, storage device and information processing method

Examples

Experimental program
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Embodiment 1

[0078] Such as figure 2 As shown, the embodiment of the present invention provides a check node computing unit, including:

[0079] A comparison module 110, configured to obtain the minimum value in the information transmitted from the variable node to the check node by comparison;

[0080] The mapping module 120 is configured to obtain the reduced minimum value or the second minimum value according to the mapping rule and the minimum value.

[0081] The comparison module 110 in this embodiment may correspond to a comparison circuit or a processing chip with a comparison function. The processing chip can be a digital processing chip, a programmable array chip, or an application processing chip. In this embodiment, the comparison circuit or the processing chip only acquires the minimum value among the information transmitted from the variable node to the check node through comparison. In this embodiment, the information transmitted from the variable node to the check node m...

Embodiment 2

[0086] Such as figure 2 As shown, the embodiment of the present invention provides a check node computing unit, including:

[0087] A comparison module 110, configured to obtain the minimum value in the information transmitted from the variable node to the check node by comparison;

[0088] The mapping module 120 is configured to obtain the reduced minimum value or the second minimum value according to the mapping rule and the minimum value.

[0089] The mapping rules include a first mapping rule; such as Figure 3A or Figure 3B As shown, the mapping module 120 in this embodiment includes:

[0090] The first mapping submodule 121 is connected to the comparison module 110, and is used to obtain the value corresponding to the minimum under the first mapping rule; wherein, the value corresponding to the minimum value is regarded as the The second minimum value in the information transmitted by the variable node to the check node;

[0091] The reduction sub-module 122 is at...

Embodiment 3

[0103] Such as figure 2 As shown, the embodiment of the present invention provides a check node computing unit, including:

[0104] A comparison module 110, configured to obtain the minimum value in the information transmitted from the variable node to the check node by comparison;

[0105] The mapping module 120 is configured to obtain the reduced minimum value or the second minimum value according to the mapping rule and the minimum value.

[0106] The mapping rules include a first mapping rule. Such as Figure 3A or Figure 3B As shown, the mapping module 120 in this embodiment includes:

[0107] The first mapping submodule 121 is connected to the comparison module 110, and is used to obtain the value corresponding to the minimum under the first mapping rule; wherein, the value corresponding to the minimum value is regarded as the The second minimum value in the information transmitted by the variable node to the check node;

[0108] The reduction sub-module 122 is a...

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Abstract

The invention discloses a check node operation unit, a check node, a storage devices and an information processing method. The check node operation unit includes a comparison module used for obtaining a minimum value in information transmitted to a check node by a variable node through comparison, and a mapping module used for obtaining a post-reduction minimum value or second smallest value according to mapping rules and the minimum value.

Description

technical field [0001] The present invention relates to the field of information technology, in particular to a check node computing unit, a check node, a storage device and an information processing method. Background technique [0002] The Low Density Parity Check code (Low Density Parity Check, LDPC) decoding algorithm is a process of iterative operation of channel information between a check node (Check Node, CN) and a variable node (Variable Node, VN). [0003] First, the channel information is transmitted to the variable node for initialization, the variable node is updated to obtain the information transmitted by the variable node to the check node, and passed to the check node, and the check node is updated to obtain C2V information, and then passed to the variable node. During the iterative process, when the check node verifies that the decoding result is correct, or when the maximum number of iterations has been reached, the decoding result is output to complete on...

Claims

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Application Information

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IPC IPC(8): H03M13/11
CPCH03M13/1137
Inventor 张喧薇黄勤王展李立华李宗旺
Owner BEIJING LENOVO CORE TECH CO LTD