Multi-cycle non-pipeline CPU debugging method based on finite state machine

A finite state machine and debugging method technology, applied in the computer field, can solve problems such as complex circuits, large consumption, CPU operating status and efficiency impact, and achieve the effect of less additional circuits

Active Publication Date: 2020-01-03
UNIV OF SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] In the process of processor design, a lot of manpower and material resources are often spent to verify the correctness of the CPU. Once a problem occurs, a reliable means is needed to locate the problem.
[0003] However, in the prior art, it is necessary to introduce more complex circuits when debugging a running CPU, and at the same time, it also has a certain impact on the running state and efficiency of the CPU

Method used

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  • Multi-cycle non-pipeline CPU debugging method based on finite state machine
  • Multi-cycle non-pipeline CPU debugging method based on finite state machine
  • Multi-cycle non-pipeline CPU debugging method based on finite state machine

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Embodiment Construction

[0018] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0019] Such as figure 1 As shown, the steps for the CPU to process each instruction are instruction fetching, decoding, execution, memory access, and write-back in sequence; the jump between steps is realized by a finite state machine;

[0020] In the embodiment of the present invention, CPU debugging is realized by introducing register A and register B. At the same time, a decision state is inserted into the finite state machine, such as figure ...

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Abstract

The invention discloses a finite state machine based multi-cycle non-flow line CPU debugging method. The method can suspend a CPU in the condition that operation sites of a CPU register bank, a program counter, a state register and other CPUs are not changed; in this state, the state of the CPU can be read, and then a debugging purpose can be achieved; and in addition, the method induces few additional circuits, and cannot affect the operation state and efficiency of the CPU in a normal working mode.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a multi-cycle non-pipeline CPU debugging method based on a finite state machine. Background technique [0002] In the processor design process, a lot of manpower and material resources are often spent to verify the correctness of the CPU. Once a problem occurs, a reliable means is needed to locate the problem. [0003] However, in the prior art, it is necessary to introduce relatively complex circuits when debugging a running CPU, and at the same time, it also has a certain impact on the running state and efficiency of the CPU. Contents of the invention [0004] The purpose of the present invention is to provide a multi-cycle non-pipeline CPU debugging method based on a finite state machine, which introduces fewer additional circuits, and does not affect the operating state and efficiency of the CPU in the normal operating mode of the CPU. [0005] The purpose of the present...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/22
CPCG06F11/2236G06F11/2273
Inventor 卢建良
Owner UNIV OF SCI & TECH OF CHINA
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