AES encryption and decryption device and method in cbc mode

Abstract

The invention discloses an advanced-encryption-standard (AEC) encryption and decryption apparatus and methods in a cipher block chaining (CBC) mode. The encryption and decryption apparatus comprises an input-output module, a feedback and accumulation module, and an AES nuclear module. The input-output module receives input data and a control signal from an upper layer and sends the processed data and control signal. The feedback and accumulation module carries out feeding back and accumulation on input and output data based on the control signal. The AES nuclear module carries out encryption and decryption on the input data according to different control signals; to be specific, the AES nuclear module carries out encryption and decryption on to-be-encrypted / decrypted data by selecting a 128-bit secret key length single mode based on an iterative operation, wherein the iterative operation each turn consists of row shifting, byte replacing, column mixing, and add round key processes. Besides, the AES nuclear module employs an encryption-decryption multiplexing combination S box structure and uses a dual-path AES message level to realize encryption and decryption. According to the invention, effects of small area and high throughput capacity are realized; and the throughput capacity of over 1 Gbps is realized in a dual-path mode by using a message-level parallel processing method.

Description

technical field [0001] The present invention relates to an AES encryption and decryption device and method, in particular to an AES encryption and decryption device and method in CBC mode with a dual-path AES feedback structure meeting the throughput requirement of 1 Gbps or more. Background technique [0002] Since the AES (Advanced Encryption Standard, Advanced Encryption Standard) algorithm was adopted by NIST as a standard algorithm in 2001, it has been adopted as an encryption algorithm by various communication systems because of its balanced advantages in terms of security, complexity, and speed. In communication occasions with higher throughput requirements, hardware implementation has a higher rate than software implementation. With the development of SOC (system on chip) and other technologies, the integration of the system is getting higher and higher, and there is a considerable demand for the realization and integration of AES chips with different throughputs and...

AI Technical Summary

Problems solved by technology

High-speed algorithms usually use a lookup table S-box, which results in a huge area and power consumption cost, and because the lookup table S-box has a high linear correlation with power, which affects its security

The design of the combined algorithm S-box often cannot achieve high throughput, and in the CBC (Cypher block chaining, cipher segment chaining) feedback mode, it is impossible to achieve real-time parallel design

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