Clock signal level shift amplitude control circuit

Abstract

The invention discloses a clock signal level shift amplitude control circuit comprising an MOS switch circuit and a work circuit, wherein the work circuit comprises one or more load driving circuits capable of realizing level shift and amplitude adjustment, and the MOS switch circuit is connected with each load driving circuit. The invention provides the clock signal level shift amplitude control circuit, the MOS transistor switch circuit is separated from the load driving work circuit, an equivalent capacitor in a load can be prevented from affecting the MOS transistor switch circuit while the level shift can be realized, and work stability of a whole clock signal level shift circuit can be improved. The clock signal level shift amplitude control circuit is capable of controlling level amplitude after level shift and enabling the level amplitude to be between zero and a maximum value.

Description

technical field [0001] The invention relates to a level displacement amplitude control circuit of a clock signal. Background technique [0002] In multi-power analog signal processing circuits, it is often necessary to level-shift the clock control signal to achieve control of analog signals with different common-mode levels, such as figure 1 As shown, in the conventional level shifting circuit, two capacitive level shifting capacitors C10, C20 and two MOS transistors M10, M20 are used, combined with an inverter to form a level shifting circuit, and one end of the load is directly connected to The common end of the drain of capacitor C20 and M20, and the other end of the load are grounded to realize the level shift. However, when the equivalent capacitance of the load Cload is large, there will be a situation of dividing the voltage with the capacitor C20, resulting in the capacitor C20 The level amplitude of the common terminal with the drain of M20 decreases, and the cond...

AI Technical Summary

Problems solved by technology

[0002] In multi-power analog signal processing circuits, it is often necessary to level-shift the clock control signal to achieve control of analog signals with different common-mode levels, such as figure 1 As shown, in the conventional level shifting circuit, two capacitive level shifting capacitors C10, C20 and two MOS transistors M10, M20 are used, combined with an inverter to form a level shifting circuit, and one end of the load is directly connected to The common end of the drain of capacitor C20 and M20, and the other end of the load are grounded to realize the level shift. However, when the equivalent capacitance of the load Cload is large, there will be a situation of dividing the voltage with the capacitor C20, resulting in the capacitor C20 The level amplitude of the common terminal with the drain of M20 decreases, and the conduction effect of the M1 tube is not good. In severe cases, the conduction failure occurs, which makes the circuit invalid; which is between zero and the maximum

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