Semiconductor device
A semiconductor and electrical conductivity technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as suppressing poor bump bonding
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no. 1 approach
[0019] figure 1 It is a figure which shows the structural example of a semiconductor device. figure 1 The shown semiconductor device 1 includes: a substrate 11; a plurality of conductive pads 12 disposed on the substrate 11; a substrate 21 facing the substrate 11 with the plurality of conductive pads 12 interposed therebetween. set in a manner; a plurality of conductive pads 22, which are arranged on the substrate 21 in a manner between the substrate 11 and the substrate 21; an insulating bonding layer 3, which connects the substrate 11 and the substrate 21 sealing; and a plurality of bumps 4. In addition, the number of conductive pads 12, conductive pads 22, and bumps 4 is not limited to figure 1 Quantity shown.
[0020] The substrate 11 may include, for example, a semiconductor substrate such as a silicon substrate, a glass substrate, a resin substrate, or a metal substrate. Furthermore, the substrate 11 may also have flexibility. Alternatively, a semiconductor element ...
no. 2 approach
[0053] Figure 8 It is a diagram showing a structural example of a semiconductor device in which semiconductor chips having penetrating electrodes such as TSVs are stacked. Figure 8 (A) is a bottom view, Figure 8 (B) is Figure 8 Sectional view of line segment A-B in (A). In addition, in Figure 8 In (A), some components are not shown for convenience. In addition, for the same components as those of the first embodiment, the description of the first embodiment can be appropriately cited.
[0054] Figure 8 (A) and Figure 8 The semiconductor device 100 shown in (B) includes: a wiring substrate 101 having a first surface and a second surface facing each other; a chip laminate 102 mounted on the first surface of the wiring substrate 101 the sealing resin layer 103, which seals between the wiring substrate 101 and the chip laminate 102; the sealing resin layer 104, which is provided to cover the chip laminate 102; and the external connection terminal 105, which is provid...
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