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Method for fabricating semiconductor package with multilayer molded conductive substrate and structure

A conductive structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of lack of circuit pattern flexibility, expensive, complex manufacturing technology, etc.

Active Publication Date: 2021-09-28
AMKOR TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition to requiring expensive and complex fabrication techniques, each of these techniques lacks flexibility in redesign of circuit patterns

Method used

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  • Method for fabricating semiconductor package with multilayer molded conductive substrate and structure
  • Method for fabricating semiconductor package with multilayer molded conductive substrate and structure
  • Method for fabricating semiconductor package with multilayer molded conductive substrate and structure

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Embodiment Construction

[0017] refer to Figure 1 to Figure 11 , a method for manufacturing a semiconductor package according to the first embodiment, and a semiconductor package 1000 manufactured using the method will be described. Figure 1 to Figure 11 A partial cross-sectional view illustrating a method of manufacturing a semiconductor package according to the first embodiment.

[0018] First, if figure 1 As shown, a first conductive pattern 110 is formed on a first surface 11 of a carrier 10 . Here, the carrier 10 including the first surface 11 further includes a second surface 12 opposite to the first surface 11 . In one embodiment, the substrate 10 has a thickness ranging from about 3 microns to 300 microns. In some embodiments, the carrier 10 may be formed of one or more of metal, silicon, glass, epoxy, or other materials known to those skilled in the art. At least the first surface 11 has been prepared and cleaned for receiving the first conductive pattern 110 .

[0019] In one embodimen...

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Abstract

A method to fabricate a semiconductor package having a multilayer molded conductive substrate and structure. In one embodiment, a method for manufacturing a semiconductor package includes providing a multilayer molded conductive structure. The multilayer molded conductive structure includes: a first conductive structure disposed on a surface of a carrier; and a first encapsulant covering at least part of the first conductive structure while other parts are exposed to In the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure, a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed to the second In a receiving space in the encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure, and in some embodiments, removing the carrier.

Description

technical field [0001] This application claims priority to U.S. Patent Application Serial No. 15 / 133,081, filed April 19, 2016, in the U.S. Patent Office, entitled "For Fabrication of a Multilayer Molded Conductive Substrate and Structure Method for Packaging Semiconductors", and the priority of Korean Patent Application No. 10-2015-0071718 filed on May 22, 2015 at the Korean Intellectual Property Office, and all Interest is its own pursuant to 35 U.S.C. §119, the contents of which are hereby incorporated by reference in their entirety. [0002] The present invention relates generally to electronic circuits, and more particularly to semiconductor packages and structures thereof, and methods of forming semiconductor packages. Background technique [0003] In accordance with recent demands for miniaturization and high performance of electronic devices, various processes have been researched and developed for providing high performance semiconductor packages. One of the proce...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/31H01L23/498H01L21/50H01L21/56
CPCH01L21/50H01L21/568H01L23/31H01L23/49822H01L23/49827H01L23/49838H01L21/4857H01L23/13H01L23/3128H01L23/36H01L24/05H01L24/13H01L24/16H01L24/32H01L24/73H01L24/81H01L24/92H01L25/0657H01L25/50H01L2224/0401H01L2224/05573H01L2224/05575H01L2224/0558H01L2224/05611H01L2224/05624H01L2224/05639H01L2224/05644H01L2224/05655H01L2224/13111H01L2224/13116H01L2224/13147H01L2224/16227H01L2224/16235H01L2224/16238H01L2224/32225H01L2224/73204H01L2224/81005H01L2224/81815H01L2224/83005H01L2224/92125H01L2225/06517H01L2225/06548H01L2225/06572H01L2225/06589H01L2924/15153H01L2924/15311H01L2924/15321H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19105H01L2924/19106H01L2924/0105H01L2224/16225H01L2924/00
Inventor 班文贝元秋亨郑季洋金本吉金即俊李钟炫
Owner AMKOR TECH INC