A transmission electron microscope sample stage loading area with the function of field effect transistor
A technology of transmission electron microscope samples and field effect transistors, which is applied to circuits, discharge tubes, electrical components, etc., can solve the problems of not being able to provide electric field effect transistors with working environments, exploring structural changes and structure-performance relationships, and being unable to use transmission electron microscopy, etc.
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Embodiment 1
[0031] Preparation of the sample loading area of the transmission electron microscope sample stage with the function of field effect transistor based on the size of 10mmX10mm, Pt electrodes, and 5 probes:
[0032] Clean the surface of the Si substrate with a 98% alcohol solution, blow it off with high-purity nitrogen, and grow a layer of SiO with a thickness of 80nm on the surface by heating and growing. 2 insulating layer, formed covered with SiO 2 Si sheet substrate with oxide layer; SiO 2 The insulating layer is etched into the same pattern as the final electrode shape, wherein the distance between the source pattern and the drain pattern is 2 μm; the gaps and gaps between the source pattern, the drain pattern and the gate pattern are etched; Deposit Pt electrodes on the source pattern, the drain pattern and the gate pattern, as the three electrodes of the source, the drain and the gate; use a diamond saw to cut the sample-loading region into probes, and obtain the follo...
Embodiment 2
[0035] The preparation of the sample loading area of the transmission electron microscope sample stage with the function of field effect transistor based on the size of 5mmX5mm, Cu electrode, and 3 probes:
[0036] Clean the surface of the Si substrate with a 98% alcohol solution, blow it off with high-purity nitrogen, and grow a layer of SiO with a thickness of 70nm on the surface by heating and growing. 2 insulating layer, formed covered with SiO 2 Si sheet substrate with oxide layer; SiO 2 The insulating layer is etched into the same pattern as the final electrode shape, wherein the distance between the source pattern and the drain pattern is 6 μm; the gaps and gaps between the source pattern, the drain pattern and the gate pattern are etched; Deposit Cu electrodes on the source pattern, drain pattern, and gate pattern as the three electrodes of source, drain, and gate; use a diamond saw to cut the sample loading area into 3 probes, each probe There are multiple field-e...
Embodiment 3
[0038] Preparation of the sample loading area of the TEM sample stage with the function of field effect transistor based on the size of 6mmX6mm, Au electrodes, and 4 probes:
[0039] Clean the surface of the Si substrate with a 98% alcohol solution, blow it off with high-purity nitrogen, and grow a layer of SiO with a thickness of 60 nm on the surface by heating and growing. 2 insulating layer, formed covered with SiO 2 Si sheet substrate with oxide layer; SiO 2 The insulating layer is etched into the same pattern as the final electrode shape, wherein the distance between the source pattern and the drain pattern is 8 μm; the gaps and gaps between the source pattern, the drain pattern and the gate pattern are etched; Deposit Au electrodes on the source pattern, drain pattern and gate pattern as the three electrodes of source, drain and gate; use a diamond saw to cut the sample loading area into 4 probes, each probe There are multiple field-effect transistor structures; the ...
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