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Semiconductor component and manufacturing method thereof

A semiconductor and component technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the difficulty of wafer-level packaging of large-size wafers, and the failure of die and wafer stack assembly , It is difficult to maintain the connection between the die and the wafer, etc.

Active Publication Date: 2016-12-07
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Wafer warpage makes it difficult to maintain the connection between the die and the wafer, resulting in the failure of the stacked assembly of the die and the wafer
The warpage problem is more obvious on large-sized wafers, making wafer-level packaging of large-sized wafers more difficult

Method used

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  • Semiconductor component and manufacturing method thereof
  • Semiconductor component and manufacturing method thereof
  • Semiconductor component and manufacturing method thereof

Examples

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Embodiment Construction

[0035] The ensuing detailed description shall refer to the contents shown in the relevant drawings, which are used to illustrate embodiments that can be implemented according to the present invention.

[0036] These examples provide sufficient detail to enable those skilled in the art to fully understand and practice the invention. Structural, logical, and electrical changes may be made in other embodiments without departing from the scope of the present invention.

[0037] Therefore, the ensuing detailed description is not intended to limit the invention. The scope of the invention is defined by its claims. It has the same meaning as the claims of the present invention, and should also belong to the scope covered by the present invention.

[0038] The drawings to which embodiments of the present invention refer are schematic diagrams and are not drawn to scale, and the same or similar features are generally described with the same reference numerals.

[0039] In this speci...

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Abstract

The invention discloses a semiconductor component which comprises a middle layer base plate comprising a front side and a back side, a rerouting layer is arranged on the front side and comprises a plurality of contact pads, a plurality of lugs which is respectively arranged on the contact pads, at least one semiconductor chip which is arranged on the front side and is electrically connected with the rerouting layer through the lugs, a wraping restran cover is arranged on the front side to cover and seal the semiconductor chip, and a plurality of through-silicon vias which pass through the middle layer base plate and are electrically connected with the rerouting layer.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a fan-out wafer level packaging and a method for manufacturing an interposer substrate. Background technique [0002] The wafer level packaging process is a technique well known to those skilled in the art. In the wafer-level packaging process, the wafer on which the integrated circuit is formed or the chip is mounted on will go through a series of processes, such as polishing, die alignment bonding, and molding, and finally cut to obtain the final product. Nowadays, the industry generally believes that the wafer-level packaging process is the most suitable technology for small-size and high-speed chip packaging. [0003] Usually, when WLP is performed, a relatively thick molding compound is used to cover the wafer and the die mounted on the wafer. Since the coefficient of thermal expansion (CTE) of the molding compound is different from that of the wafer, a package made ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L21/48
CPCH01L2224/97H01L23/4952H01L21/4825
Inventor 罗翊仁施能泰
Owner MICRON TECH INC