FPGA anti-single event reversal fast refresh circuit and method based on ECC error correction code

Abstract

The invention relates to an SEU (single event upset)-resistant fast refreshing circuit and method applied to an FPGA (field programmable gate array) and based on ECCs (error correcting codes). The method comprises steps as follows: for any one frame address generated by a frame address generation module, a read-write control module reads data frames through an ICAP (internal configuration access port) of the FPGA, only reads frame data of the current frame address every time and writes the read data frame into a frame caching module; after a frame synchronization signal received by a working state control and error analysis module from a frame ECC interface of the FPGA becomes higher from lower, the ECCs of the current data frame are read, and the upset position in the data frame is calculated; a frame error correction module reads a segment of SEU data from the frame caching module according to the upset position and performs negation on the upset position, correct data after error correction is obtained and is written into the frame caching module again, the correct data frame is written into the current frame address of the FPGA again by the read-write control module, and accordingly, SEU-resistant error correction of the FPGA is completed.

Description

technical field [0001] The invention relates to the field of reliability design of FPGA circuits in space payloads, in particular to an FPGA anti-single event flip fast refresh circuit and method based on ECC error correction codes. Background technique [0002] Virtex-4 and Virtex-5 series FPGAs are SRAM-type FPGAs. At present, the configuration refresh circuit of SRAM-type FPGAs mostly uses anti-fuse FPGAs as the main control chip, which are connected to PROM and FPGA respectively to control the normal loading program and the dynamic after normal operation. refresh. Among them, the anti-fuse FPGA adopts A54SX72A and other series FPGAs. The chip is bulky and takes up valuable space on the printed board. In addition, when designing the circuit, it is necessary to disconnect the loading connection between the FPGA and the PROM. The anti-fuse FPGA spans Connected at both ends of the disconnection, compared with the original circuit design, there are many changes, the technica...

AI Technical Summary

Problems solved by technology

"A CRC Verification Method for SRAM-type FPGA Configuration Refresh" 201410783776.5 also uses an anti-fuse FPGA as the control circuit, and uses the CRC verification method to detect whether a single event flip occurs in the FPGA. This verification method not only increases the program The design is difficult, and the verification result cannot provide the location of the single event flip in the data frame, so it is not suitable for application on Virtex-4 and Virtex-5 series FPGAs

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