A high-speed DAC synchronization method and circuit

Abstract

The embodiment of the invention discloses a high-speed DAC synchronization method and circuit. The method comprises the steps that an FPGA controls the initialization of the first high-speed DAC to the Nth high-speed DAC, and resets the first high-speed DAC to the Nth high-speed DAC if determining the initialization failure of at least one high-speed DAC; the FPGA monitors the synchronization states of the first high-speed DAC to the Nth high-speed DAC, and controls a phase discrimination module to carry out phase discrimination on output clocks of the first high-speed DAC to the Nth high-speed DAC after determining synchronization success; and then, the FPGA uses the output clock of any high-speed DAC in the first high-speed DAC to the Nth high-speed DAC as a data clock of the FPGA, and transmits data to the first high-speed DAC to the Nth high-speed DAC. According to the high-speed DAC synchronization method and circuit disclosed by the embodiment of the invention, the input clocks and the output clocks of the first high-speed DAC to the Nth high-speed DAC are respectively monitored, and when it is detected that the phase difference of the input clocks or the output clocks is too large, corresponding operations are carried out on the input clocks, the output clocks and the first high-speed DAC to the Nth high-speed DAC, therefore the synchronous output problem and the clock delay problem of the first high-speed DAC to the Nth high-speed DAC are effectively solved.

Description

technical field [0001] The invention relates to the field of digital signal processing and communication, in particular to a high-speed DAC synchronization method and circuit. Background technique [0002] In recent years, satellite communication technology has developed rapidly, and the transmission rate and bandwidth of relay satellites, remote sensing satellites, communication satellites and other satellites are also increasing day by day. Traditional modulation and demodulation technology can no longer meet the needs of current satellite communications, so the development of higher-speed modulation and demodulation technology has become a hot spot in satellite application technology. [0003] With the development of high-speed modulation technology, new challenges have been raised to the hardware of the modulator. As a core component of the modulator, a digital-to-analog converter (DAC for short) has become a key to limit and restrict the speed of the modulator. In rec...

AI Technical Summary

Problems solved by technology

In recent years, high-speed DAC chips have emerged continuously, which has gradually improved the performance of high-speed modulators, but their existing problems are also more obvious: when multiple high-speed DACs work at the same time, it is difficult to guarantee synchronization; high-speed DACs have high requirements for input clock stability. Each channel is prone to clock delay

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