A chip input pin testing method and device

[0042] In order to describe in detail the technical content, structural features, achieved objectives and effects of the technical solution, the following detailed descriptions are given in conjunction with specific embodiments and accompanying drawings.

[0043] See figure 1 , A schematic diagram of a chip input pin testing device according to an embodiment of the present invention.

[0044] The chip includes at least one pin to be tested, and the device includes an output value setting unit 101, a mode setting unit 102, a pin setting unit 103, an excitation generating unit 104, a sampling unit 105, a storage unit 106, an output unit 107, and a calibration unit. 验 Unit 108. A pin, also called a pin, is the connection between the internal circuit of the integrated circuit (chip) and the peripheral circuit. All the pins constitute the external interface of the chip.

[0045] The output value setting unit 101 is used to set an output preset value;

[0046] The mode setting unit 102 is used to receive a test signal to put the chip in a test mode, and the pin setting unit 103 is used to set the pin under test of the chip to an input state;

[0047] The excitation generating unit 104 is used to generate an excitation sequence and transmit the excitation sequence to the pin under test of the chip; the generated excitation sequence is the same as the output preset value, and the excitation sequence includes at least one digit value. The pin corresponds to a value in the received excitation sequence;

[0048] The mode setting unit 102 is also used to receive a sampling signal to put the chip in a sampling mode, and the sampling unit 105 is used to sample the corresponding received value of each pin to be tested, and store the sampling result in the storage unit 106 ;

[0049] The mode setting unit 102 is used to receive the sampling output signal and put the chip in the sampling output mode, and the output unit 107 is used to transmit the sampling result stored in the storage unit 106 to the verification unit 108 through the output pin. The test pin corresponds to an output pin, and the output pin is used to output a value;

[0050] The verification unit 108 is used to determine whether the value output by the output unit is the same as the output preset value, if so, the verification is passed, otherwise the verification is not passed.

[0051] When using the chip input pin test device, the output value setting unit 101 first sets the output preset value. The output preset value is the ideal output value. If the output value through the pin of the chip is the same as the output preset value, it indicates that the pin function of the chip is in line with expectations, otherwise the function of at least one pin of the chip is impaired. The output setting value can be input by technicians according to actual needs.

[0052] Then the mode setting unit 102 receives the test signal to put the chip in the test mode, and the pin setting unit 103 sets the pin under test of the chip to the input state. The mode setting unit can be realized by the corresponding switch logic circuit. The test mode is relative to the function mode. When the chip is in the test mode, the control signal of the test mode is set to high level, and the function mode (normal working mode) The control signal is set to low level. In this embodiment, the object of the test is the pin in the input state, that is, whether the input function of the test chip pin is normal, so the pin to be tested needs to be set to the input state. The pin setting unit can be realized by the three-state output control circuit. In the test mode, the value of the three-state control terminal is the high-impedance output state, and the output terminal of the PAD's three-state output control circuit is the high-impedance state. The pin is driven by the excitation sequence and is in the input state.

[0053] Then the excitation generating unit 104 generates an excitation sequence, and transmits the excitation sequence to the pin under test of the chip. The generated excitation sequence is the same as the output preset value. The excitation sequence includes at least one bit value, and each pin to be tested corresponds to one bit value in the received excitation sequence. In this embodiment, the excitation sequence is a sequence composed of the value "0" or "1". For example, if the number of pins to be tested on a certain chip is 20, the input excitation sequence is a string of 20 bits composed of "0" or "1", and each pin to be tested is used to receive a "0" Or "1" value. Set the excitation sequence to be the same as the output preset value, so that after the excitation sequence is transmitted through the pin to be tested, the output value is compared with the output preset value to determine whether the input function of the pin to be tested is normal .

[0054] Then the mode setting unit 102 receives the sampling signal and puts the chip in the sampling mode. The sampling unit 105 samples the value received corresponding to each pin to be tested, and stores the sampling result in the storage unit 106. The chip is in sampling mode, which means that the pin under test of the chip has completely received the excitation sequence, that is, each pin under test has received a corresponding value of the excitation sequence. In terms of circuit implementation, the control signal of the test mode can be set to a high level. When the chip is in the test mode, the chip is in the sampling mode by setting the control signal of the sampling mode to a high level. Preferably, the control signal of the sampling mode can be realized by separately setting (different from the test control circuit) a sampling control circuit.

[0055] In this embodiment, the storage unit 106 is a register set, which includes a plurality of registers arranged in a preset order, and each register is used to store a value sampled from a pin to be tested. The sampling unit can be implemented by a sampling circuit, which samples the value received by each pin to be tested, and stores the sampled value in the register corresponding to the pin to be tested. Such as figure 2 , Is a schematic diagram of a chip input pin test device. The chip contains multiple pins to be tested. Each pin to be tested corresponds to a self-test circuit. The schematic diagram of the self-test circuit is as follows image 3 Shown. For example, the number of pins to be tested is 3, including pin A to be tested, pin B to be tested and pin C to be tested; pin A to be tested corresponds to register a, pin B to be tested corresponds to register b, Pin C corresponds to register c; the input excitation sequence is "101", where the value received by pin A to be tested is "1", the value received by pin B to be tested is "0", and the pin to be tested The value received by C is "1", and after sampling the value received by the pin to be tested, the sampling unit will assign the value of register a to "1", the value of register b to "0", and the value of register c to The value assignment is "1".

[0056] Then, the mode setting unit 102 receives the sampling output signal and puts the chip in the sampling output mode, and the output unit 107 transmits the sampling result stored in the storage unit 106 to the verification unit 108 through the output pin. The chip is in the sampling output mode, which means that the value received by the pin under test of the chip has been sampled, that is, the value of the one-bit excitation sequence received on each pin under test is stored in the corresponding register. The test mode is relative to the functional mode under normal working conditions, including sampling mode and sampling output mode. In terms of circuit implementation, a sampling control circuit and a test control circuit can be used to switch between the sampling output mode and the sampling mode. The sampling control circuit is used to input the sampling mode control signal, and the test control circuit is used to input the test mode. control signal. The test mode control signal is set to high level, and the sampling mode control signal is low, indicating that the chip is in sampling output mode; the test mode control signal is high and the sampling mode control signal is high, indicating that the chip is in sampling mode.

[0057] In this embodiment, each pin to be tested corresponds to an output pin, and the output pin is used to output a one-bit value. The present invention tests the input function of the chip pins, but each pin can only be in a certain state (either input or output) at the same time. When the pin to be tested is in the input state, each pin to be tested can receive the value of a stimulus sequence; when the value of each pin to be tested needs to be output from the register, it needs to be completed through the output pin test. The output pin is a pin that has passed an output test and has a good output function. In this way, it can be ensured that the value output from the register will not change due to damage to the output function of the pin or cannot be output accurately. For example, a certain chip has 100 pins, 50 of which are to be tested, and the other 50 pins have been tested to have normal output functions. You can match the pins to be tested with the pins with normal output functions. The value of the pin, which is sampled and stored in the register corresponding to the pin, is output through the output pin corresponding to the pin. Another example is that a chip has 101 pins, 51 of which have input functions to be tested, and 50 pins have been tested and output functions are normal. Only 50 pins can be tested in each clock cycle. Two clock cycles are used to complete the above-mentioned 51-pin input function test. The first clock cycle is the same as the previous example, and will not be repeated here; the second clock cycle is from 50 output functions that are normal. Select one of the pins to correspond to the pin to be tested that has not yet been tested for input functions. The value stored in the register corresponding to the pin to be tested that has not yet undergone the input function test is output through the selected pin with normal output function.

[0058] Then the verification unit 108 determines whether the value output by the output unit is the same as the output preset value, and if so, the verification is passed, otherwise the verification is not passed. In this embodiment, the verification unit and the stimulus generation unit are a chip test machine, which is a professional chip test equipment that can be used to generate test stimuli and observe and check the response sequence output by the chip. In other embodiments, the verification unit is also used to identify the difference between the value output by the output unit and the output preset value when it is determined that the value output by the output unit is different from the output preset value. The number of digits.

[0059] For example, the number of pins to be tested is 3, the output preset value is "101", the excitation sequence is also "101", and the output value of the output unit is "111", because the second input and output of the excitation sequence are not If it matches, it will identify that there is a problem with the second one. Also, because the second digit value is output from register b, and the pin to be tested corresponding to register b is pin b, it indicates that there is a problem with pin b, and technicians can perform further testing on pin b. Take relevant measures to deal with it.

[0060] In some embodiments, the number of the chips is multiple, and the chip models are the same, and the excitation generating unit is used to generate excitation sequences and transmit the generated excitation sequences in parallel to different chips of the same model to be tested. Pin. The test machine can output excitation sequence to the same type of chip at the same time to speed up the test efficiency. For example, there are three chips A, B, and C to be tested, and the models of the three chips A, B, and C are exactly the same, so that the test machine can test these three chips at the same time through the same excitation sequence. Assuming that the number of pins to be tested corresponding to chips A, B, and C is 50, the test machine will generate a 50-bit excitation sequence and send the generated excitation sequence to chip A, chip B, and chip C, respectively. Each pin of each chip corresponds to a bit value in the receiving excitation sequence, and the specific test procedure of each chip is as described in the foregoing manner, and will not be repeated here.

[0061] The above device can switch the current mode of the chip according to the control signal, and input the excitation sequence to the pin under test of the chip, and then store the value received by the pin under test in the storage unit through the sampling unit, and then pass the test The output pin corresponding to the pin (the other pin with good output function corresponding to the pin to be tested) outputs the value of the storage unit, and the output value is mirrored and compared with the preset output value in the verification unit, thereby automatically Check whether the input function of the pin under test of the chip is normal, so that the test can be performed when the chip is in the bare chip stage, which is equivalent to the way of the whole machine test, which greatly reduces the test cost. In addition, the input excitation sequence can be customized and confirmed according to actual needs, which has high flexibility and fault detection coverage.

[0062] See Figure 4 , Is a schematic diagram of a method for testing chip input pins according to an embodiment of the present invention. The method is applied to a chip input pin test device, the chip includes at least one pin to be tested, and the device includes an output value setting unit, a mode setting unit, a pin setting unit, an excitation generating unit, a sampling unit, and a storage unit , Output unit and check unit; the method includes the following steps:

[0063] First, go to step S301, the output value setting unit sets the output preset value. The output preset value is the ideal output value. If the output value through the pin of the chip is the same as the output preset value, it indicates that the pin function of the chip is in accordance with expectations, otherwise the function of at least one pin of the chip is impaired. The output setting value can be input by technicians according to actual needs.

[0064] Then it proceeds to step S302. The mode setting unit receives the test signal and puts the chip in the test mode, and the pin setting unit sets the pin under test of the chip to the input state. The mode setting unit can be realized by the corresponding switch logic circuit. The test mode is equivalent to the functional mode. When the chip is in the test mode, the control signal of the test mode is set to high level, and the function mode (normal working mode) The control signal is set to low level. In this embodiment, the object of the test is the pin in the input state, that is, whether the input function of the test chip pin is normal, so the pin to be tested needs to be set to the input state. The pin setting unit can be realized by the three-state output control circuit. In the test mode, the value of the three-state control terminal is the high-impedance output state, and the output terminal of the PAD's three-state output control circuit is the high-impedance state. The pin is driven by the excitation sequence and is in the input state.

[0065] Then go to step S303, the excitation generating unit generates an excitation sequence, and transmits the excitation sequence to the pin under test of the chip. The generated excitation sequence is the same as the output preset value, the excitation sequence includes at least one bit value, and each pin to be tested corresponds to one bit value in the received excitation sequence. In this embodiment, the excitation sequence is a sequence composed of the value "0" or "1". For example, if the number of pins to be tested on a certain chip is 20, the input excitation sequence is a string of 20 bits composed of "0" or "1", and each pin to be tested is used to receive a "0" Or "1" value. Set the excitation sequence to be the same as the output preset value, so that after the excitation sequence is transmitted through the pin to be tested, the output value is compared with the output preset value to determine whether the input function of the pin to be tested is normal .

[0066] Then enter step S304, the mode setting unit receives the sampling signal and puts the chip in the sampling mode. The sampling unit samples the value received corresponding to each pin to be tested, and stores the sampling result in the storage unit. The chip is in sampling mode, which means that the pin under test of the chip has completely received the excitation sequence, that is, each pin under test has received a corresponding value of the excitation sequence. The control signal of the sampling mode can be set to high level. Set the control signal of the test mode to low level, so that the chip is in sampling mode.

[0067] In this embodiment, the storage unit is a register group, the register group includes a plurality of registers arranged in a preset order, and each register is used to store a value sampled from a pin to be tested. The sampling unit can be implemented by a sampling circuit, which samples the value received by each pin to be tested, and stores the sampled value in the register corresponding to the pin to be tested. For example, the number of pins to be tested is 3, including pin A to be tested, pin B to be tested and pin C to be tested; pin A to be tested corresponds to register a, pin B to be tested corresponds to register b, Pin C corresponds to register c; the input excitation sequence is "101", where the value received by pin A to be tested is "1", the value received by pin B to be tested is "0", and the pin to be tested The value received by C is "1", and after sampling the value received by the pin to be tested, the sampling unit will assign the value of register a to "1", the value of register b to "0", and the value of register c to The value assignment is "1".

[0068] Then enter step S305, the mode setting unit receives the sampling output signal, puts the chip in the sampling output mode, and the output unit transmits the sampling result stored in the storage unit to the verification unit through the output pin. The chip is in the sampling output mode, which means that the value received by the pin under test of the chip has been sampled, that is, the value of the one-bit excitation sequence received on each pin under test is stored in the corresponding register. The test mode is relative to the functional mode under normal working conditions, including sampling mode and sampling output mode. In terms of circuit implementation, a sampling control circuit and a test control circuit can be used to switch between the sampling output mode and the sampling mode. The sampling control circuit is used to input the sampling mode control signal, and the test control circuit is used to input the test mode. control signal. The test mode control signal is set to high level, and the sampling mode control signal is low, indicating that the chip is in sampling output mode; the test mode control signal is high and the sampling mode control signal is high, indicating that the chip is in sampling mode.

[0069] In this embodiment, each pin to be tested corresponds to an output pin, and the output pin is used to output a one-bit value. The present invention tests the input function of the chip pins, but each pin can only be in a certain state (either input or output) at the same time. When the pin to be tested is in the input state, each pin to be tested can receive the value of a stimulus sequence; when the value of each pin to be tested needs to be output from the register, it needs to be completed through the output pin test. The output pin is a pin that has passed an output test and has a good output function. In this way, it can be ensured that the value output from the register will not change due to damage to the output function of the pin or cannot be output accurately. For example, a certain chip has 100 pins, 50 of which are to be tested, and the other 50 pins have been tested to have normal output functions. You can match the pins to be tested with the pins with normal output functions. The value of the pin, which is sampled and stored in the register corresponding to the pin, is output through the output pin corresponding to the pin. Another example is that a chip has 101 pins, 51 of which have input functions to be tested, and 50 pins have been tested and output functions are normal. Only 50 pins can be tested in each clock cycle. Two clock cycles are used to complete the above-mentioned 51-pin input function test. The first clock cycle is the same as the previous example, and will not be repeated here; the second clock cycle is from 50 output functions that are normal. Select one of the pins to correspond to the pin to be tested that has not yet been tested for input functions. The value stored in the register corresponding to the pin to be tested that has not yet undergone the input function test is output through the selected pin with normal output function.

[0070] Then go to step S306, the verification unit judges whether the value output by the output unit is the same as the output preset value, if yes, go to step S307 to pass the verification, otherwise go to step S308 to fail the verification. In this embodiment, the verification unit and the excitation generating sequence are a chip testing machine, which is a professional chip testing equipment that can be used to generate test excitations and observe and check the response sequence output by the chip. In other embodiments, the verification unit is also used to identify the difference between the value output by the output unit and the output preset value when it is determined that the value output by the output unit is different from the output preset value. The number of digits.

[0071] For example, the number of pins to be tested is 3, the output preset value is "101", the excitation sequence is also "101", and the output value of the output unit is "111", because the second input and output of the excitation sequence are not If it matches, it will identify that there is a problem with the second one. Also, because the second digit value is output from register b, and the pin to be tested corresponding to register b is pin b, it indicates that there is a problem with pin b, and technicians can perform further testing on pin b. Take relevant measures to deal with it.

[0072] In some embodiments, the number of the chips is multiple, and the chip types are the same, and the method includes: an excitation generating unit generates an excitation sequence, and the generated excitation sequence is transmitted in parallel to the waiting sequence of different chips of the same model. Test pin. The test machine can output excitation sequence to the same type of chip at the same time to speed up the test efficiency. For example, there are three chips A, B, and C to be tested, and the models of the three chips A, B, and C are exactly the same, so that the test machine can test these three chips at the same time through the same excitation sequence. Assuming that the number of pins to be tested corresponding to chips A, B, and C is 50, the test machine will generate a 50-bit excitation sequence and send the generated excitation sequence to chip A, chip B, and chip C, respectively. Each pin of each chip corresponds to a bit value in the receiving excitation sequence, and the specific test procedure of each chip is as described in the foregoing manner, and will not be repeated here.

[0073] The above method can switch the current mode of the chip according to the control signal, and input the excitation sequence to the pin under test of the chip, and then store the value received by the pin under test in the storage unit through the sampling unit, and then pass the test The output pin corresponding to the pin (the other pin with good output function corresponding to the pin to be tested) outputs the value of the storage unit, and the output value is mirrored and compared with the preset output value in the verification unit, thereby automatically Check whether the input function of the pin under test of the chip is normal, so that the test can be performed when the chip is in the bare chip stage, which is equivalent to the way of the whole machine test, which greatly reduces the test cost. In addition, the input excitation sequence can be customized and confirmed according to actual needs, which has high flexibility and fault detection coverage.

[0074] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply one of these entities or operations. There is any such actual relationship or order between. Moreover, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements not only includes those elements, but also includes those that are not explicitly listed. Other elements listed, or also include elements inherent to this process, method, article or terminal device. Without more restrictions, the elements defined by the sentence "including..." or "including..." do not exclude the existence of other elements in the process, method, article, or terminal device that includes the elements. In addition, in this article, "greater than", "less than", "exceeds", etc. are understood to not include the number; "above", "below", "within", etc. are understood to include the number.

[0075] Those skilled in the art should understand that the foregoing embodiments may be provided as methods, devices, or computer program products. These embodiments may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. All or part of the steps in the methods involved in each of the above embodiments can be completed by a program instructing relevant hardware. The program can be stored in a storage medium readable by a computer device and used to execute the methods described in the above embodiments. All or part of the steps described. The computer equipment includes, but is not limited to: personal computers, servers, general-purpose computers, special computers, network equipment, embedded devices, programmable devices, smart mobile terminals, smart home devices, wearable smart devices, vehicle-mounted smart devices, etc.; The storage medium includes but is not limited to: RAM, ROM, magnetic disk, magnetic tape, optical disk, flash memory, U disk, mobile hard disk, memory card, memory stick, network server storage, network cloud storage, etc.

[0076] The foregoing embodiments are described with reference to the flowcharts and/or block diagrams of the methods, devices (systems), and computer program products according to the embodiments. It should be understood that each process and/or block in the flowchart and/or block diagram, and the combination of processes and/or blocks in the flowchart and/or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of the computer device to generate a machine, so that the instructions executed by the processor of the computer device are generated for realizing the process Figure one Process or multiple processes and/or boxes Figure one A device with functions specified in a block or multiple blocks.

[0077] These computer program instructions can also be stored in a computer device readable memory that can guide the computer device to work in a specific manner, so that the instructions stored in the computer device readable memory produce an article of manufacture including the instruction device, and the instruction device is implemented in the process Figure one Process or multiple processes and/or boxes Figure one Function specified in a box or multiple boxes.

[0078] These computer program instructions can also be loaded on the computer equipment, so that a series of operation steps are executed on the computer equipment to produce computer-implemented processing, so that the instructions executed on the computer equipment provide the Figure one Process or multiple processes and/or boxes Figure one Steps of functions specified in a box or multiple boxes.

[0079] Although the foregoing embodiments have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept, so the foregoing is only the implementation of the present invention For example, this does not limit the scope of patent protection of the present invention. Any equivalent structure or equivalent process transformation made by using the content of the description and drawings of the present invention, or directly or indirectly applied to other related technical fields, shall be included in the same. The invention is within the scope of patent protection.