Circuit for transistor level implementation scheme of five input end combination logical circuit

Abstract

The invention discloses a circuit for a transistor level implementation scheme of a five input end combination logical circuit. The circuit comprises a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode and the like, a grid electrode of the first triode is connected with a grid electrode of the sixth triode, a source electrode of the first triode is connected with a drain electrode of the second triode, a grid electrode of the second triode is connected with a grid electrode of the seventh triode, a source electrode of the second triode is connected with a drain electrode of the third triode, a grid electrode of the third triode is connected with a grid electrode of an eighth triode, a grid electrode of the fourth triode is connected with a grid electrode of a ninth triode, a source electrode of the fourth triode is connected with a drain electrode of the fifth triode, and a grid electrode of the fifth triode is connected with a grid electrode of a thirteenth triode. Accordingly, the number of transistors is reduced, the purpose of reducing the number of the transistors is achieved, and finally the purpose of greatly reducing the silicon area occupied by the same logical function is achieved.

Description

technical field [0001] The invention relates to a combinational logic circuit, in particular to a circuit of a transistor-level realization scheme of a five-input terminal combinational logic circuit. Background technique [0002] There are the following disadvantages and deficiencies in the current circuit for implementing the transistor-level implementation scheme of the five-input combinational logic circuit in the prior art: [0003] First, the circuit is complex and requires a large number of logic gates [0004] Prior art will realize logic Y=~(A+B+C+D+E), through hardware description language Verilog code compiling, can be as follows after synthesis then figure 2 Shown: It calls 2 inverters, 1 3-input NAND gate and 2 2-input NOR gates. [0005] Second, the signal transmission delay is large [0006] When the signal is transmitted through the three-level gate, due to the inherent delay of the gate itself, the total transmission delay from input to output increases. ...

AI Technical Summary

Problems solved by technology

[0005] Second, the signal transmission delay is large

The transmission delay from input to output is too large, and it will be fatal for circuits with high frequency, which are very concerned about the

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