Circuit for transistor level implementation scheme of five input end combination logical circuit

[0016] Hereinafter, preferred embodiments of the present invention are given in conjunction with the drawings to illustrate the technical solutions of the present invention in detail.

[0017] Such as figure 1 As shown, the circuit of the transistor-level implementation scheme of the five-input combinational logic circuit of the present invention includes a first triode Q1, a second triode Q2, a third triode Q3, a fourth triode Q4, and a fifth triode. The transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, the thirteenth transistor Q10, the gate and the first transistor Q1 The gate of the six transistor Q6 is connected, the source of the first transistor Q1 is connected to the drain of the second transistor Q2, the gate of the second transistor Q2 and the gate of the seventh transistor Q7 are connected Connected, the source of the second transistor Q2 is connected to the drain of the third transistor Q3, the gate of the third transistor Q3 is connected to the gate of the eighth transistor Q8, and the third transistor Q3 The source of the fourth transistor Q4 is connected to the drain of the fourth transistor Q4, the gate of the fourth transistor Q4 is connected to the gate of the ninth transistor Q9, and the source of the fourth transistor Q4 is connected to the fifth transistor. The drain of the transistor Q5 is connected, the gate of the fifth transistor Q5 is connected to the gate of the thirteenth transistor Q10, the source of the fifth transistor Q5, the drain of the sixth transistor Q6, and the seventh The drain of the transistor Q7, the drain of the eighth transistor Q8, the drain of the ninth transistor Q9 and the drain of the thirteenth transistor Q10 are connected, and the source of the sixth transistor Q6, The source of the seventh transistor Q7, the source of the eighth transistor Q8, the source of the ninth transistor Q9, and the source of the thirteenth transistor Q10 are connected and grounded.

[0018] The first triode Q1, the second triode Q2, the third triode Q3, the fourth triode Q4, and the fifth triode Q5 are all PMOS transistors.

[0019] The sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, and the thirteenth transistor Q10 are all NMOS transistors.

[0020] The working principle of the present invention is as follows: the present invention can make the implementation scheme into a standard cell (standard cell), so as to facilitate the call in future use.

[0021] In summary, the present invention reduces the number of transistors. The number of transistors is reduced from 18 to 10. This achieves the purpose of reducing the number of transistors, and finally achieves the goal of greatly reducing the silicon area occupied by the same logic function. .

[0022] The specific embodiments described above further describe the technical problems, technical solutions, and beneficial effects solved by the present invention in further detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit In the present invention, any modification, equivalent replacement, improvement, etc., made within the spirit and principle of the present invention should be included in the protection scope of the present invention.