Circuit for achieving transistor level implementation scheme of six-input-end combinational logic circuit

Abstract

The invention discloses a circuit for achieving a transistor level implementation scheme of a six-input-end combinational logic circuit. The circuit comprises a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode and the like; the grid electrode of the first triode is connected with the grid electrode of the seventh triode, the source electrode of the first triode, the source electrode of the second triode and the source electrode of the third triode are connected with the drain electrode of the fourth triode, the drain electrode of the fifth triode and the drain electrode of the six triode respectively, and the drain electrode of the first triode, the drain electrode of the second triode and the drain electrode of the third triode are connected with one another. The technical purpose of providing the circuit for achieving the transistor level implementation scheme of the six-input-end combinational logic circuit is achieved, the transistor quantity is decreased, the purpose of decreasing the transistor quantity is achieved, and the purpose that the silicon wafer area occupied for achieving the same logic function is significantly decreased is finally achieved.

Description

technical field [0001] The present invention relates to a combinational logic circuit, in particular to a circuit of a transistor-level realization scheme of a six-input terminal combinational logic circuit. Background technique [0002] There are the following disadvantages and deficiencies in the circuits of the prior art for implementing the transistor-level implementation scheme of the six-input combinational logic circuit: [0003] First, the circuit is complex and requires a large number of logic gates [0004] The prior art needs to realize logic Y=~((A+B) (C+D) (E+F)), edited by the hardware description language Verilog code, then it will be as follows after synthesis figure 2 Shown: It is implemented in three stages, which calls 1 inverter, 1 3-input NOR gate and 3 2-input NOR gates. [0005] Second, the signal transmission delay is large [0006] When the signal is transmitted through the three-level gate, due to the inherent delay of the gate itself, the total ...

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Problems solved by technology

[0005] Second, the signal transmission delay is large

The transmission delay from input to output is too large, and it will be fatal for circuits with high frequency, which are very concerned about the signal delay.

[0007] Third, the required circuit costs are high

[0008] Since the existing circuit uses 1 inverter (1PMOS+1NMOS, 2 transistors in total), 1 3-input NOR gate (3PMOS+3NMOS, 6 transistors in total), and 3 2-input NOR gates (2PMOS+ 2NMOS with a total of 4 transistors), which generally requires 20 transistors. Due to the large number of transistors, the silicon chip area occupied by it is relatively large

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