Circuit of transistor-grade realizing solution of five-input-end combined logic circuit

Abstract

The invention discloses a circuit of a transistor-grade realizing solution of a five-input-end combined logic circuit. The circuit comprises a first triode, a second triode, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode, a ninth triode and a tenth triode. The drain electrode of the first triode is connected with the drain electrode of the second triode. The gate electrode of the first triode is connected with the gate electrode of the sixth triode. The source electrode of the first triode is connected with the source electrode of the second triode and the drain electrode of the third triode. The gate electrode of the second triode is connected with the gate electrode of the seventh triode. The gate electrode of the third triode is connected with the gate electrode of the eighth triode. The source electrode of the third triode is connected with the drain electrode of the fourth triode. The gate electrode of the forth triode is connected with the gate electrode of the ninth triode. The circuit according to the invention has advantages of reducing number of transistors, realizing a purpose of reducing the number of transistors, and finally realizing a purpose of greatly reducing silicon chip area occupied for realizing the same logical function.

Description

technical field [0001] The invention relates to a combinational logic circuit, in particular to a circuit of a transistor-level realization scheme of a five-input terminal combinational logic circuit. Background technique [0002] There are the following disadvantages and deficiencies in the current circuit for implementing the transistor-level implementation scheme of the five-input combinational logic circuit in the prior art: [0003] 1. The circuit is complex and requires a large number of logic gates [0004] Prior art needs to realize logic Y=~(A·B+C+D+E), compiling through hardware description language Verilog code, then after synthesis, it will be as follows figure 2 Shown: It calls 2 inverters, a 3-input NAND gate, a 2-input NAND gate, and a 2-input NOR gate. [0005] Second, the signal transmission delay is large [0006] When the signal is transmitted through the three-level gate, due to the inherent delay of the gate itself, the total transmission delay from i...

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Problems solved by technology

[0005] Second, the signal transmission delay is large

The transmission delay from input to output is too large, and it will be fatal for circuits with high frequency, which are very concerned about the signal delay.

[0007] 3. The cost of the required circuit is high

[0008] Since the existing circuit uses 2 inverters (1PMOS+1NMOS, a total of 2 transistors), a 3-input NAND gate (3PMOS+3NMOS, a total of 6 transistors), a 2-input NAND gate (2PMOS+ 2NMOS with a total of 4 transistors) and a 2-input NOR gate (2PMOS+2NMOS with a total of 4 transistors), which generally requires 2*2+1*6+2*4=18 transistors, because the number of transistors is relatively large More, resulting in a larger area of ​​the silicon chip occupied

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