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Method of rapidly increasing chip verification random regression coverage rate based on linear learning

A coverage and linear technology, which is applied in the field of rapidly improving the random regression coverage of chip verification based on linear learning, can solve the problems of increased workload, repetition, and time-consuming, so as to improve analysis and increase and shorten the time spent Effect

Inactive Publication Date: 2017-05-31
SUZHOU CENTEC COMM CO LTD
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  • Description
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  • Application Information

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Problems solved by technology

Due to the large amount of code in large-scale chip design, manually analyzing the codes that are not covered in the coverage one by one not only takes a lot of time, but also inevitably repeats, and it is easy to increase the workload due to analysis errors , and may even miss validation errors

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  • Method of rapidly increasing chip verification random regression coverage rate based on linear learning
  • Method of rapidly increasing chip verification random regression coverage rate based on linear learning

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Embodiment Construction

[0024] In view of the deficiencies in the prior art, the inventor of this case was able to propose the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0025] The embodiment of the present invention provides a method for quickly improving code coverage, which specifically includes:

[0026] a. Analyze the logic code related to the function point to be covered, and obtain the incentive combination that can cover the function point;

[0027] Scripts can be used to analyze and parse the statements of different logical operators in the code to be covered, and obtain the incentive combination that can reach the code that needs to be covered;

[0028] b. Establish the corresponding logical tree according to the logical operators;

[0029] Establish a corresponding tree structure according to the logical operators in the code to be cov...

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Abstract

The present invention discloses a method of rapidly increasing chip verification random regression coverage rate based on linear learning. The method comprises the steps of analyzing logical codes relevant to a function point to be covered, and obtaining excitation combinations which can cover the function point; establishing a corresponding logic tree according to logical operators of the logical codes; calculating the corresponding path length of each excitation combination in the logic tree; selecting the excitation combination corresponding to the shortest path based on the linear principle; and constraining an input excitation according to the selected excitation combination. By adoption of the technical scheme, the time for increasing the coverage rate in the verification convergence phase can be largely shortened, and efficiency of analyzing and increasing the code coverage rate by verification people can be improved.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to a method for rapidly improving the random regression coverage of chip verification based on linear learning. Background technique [0002] In the large-scale and ultra-large-scale chip verification process, in order to ensure that all the functional points of the design are verified, checking code coverage is one of the important means to verify the quality of verification. However, due to the large amount of code and the large randomness of the verification input stimulus, in order to obtain a higher coverage rate, it is necessary to continuously modify the constraint range of the input stimulus during verification. Every time the constraint range is modified, it is necessary to collect and analyze the coverage again. The collection coverage of so many iterations greatly prolongs the verification cycle and consumes a lot of human resources. Therefore, how to quickly im...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/398
Inventor 江源唐飞周磊
Owner SUZHOU CENTEC COMM CO LTD
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