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A finfet device integrated with tfet and its preparation method

A device, N-type technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problem of low current and achieve cost-saving effects

Active Publication Date: 2019-11-22
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But the disadvantage is that the current is lower when it is turned on

Method used

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  • A finfet device integrated with tfet and its preparation method
  • A finfet device integrated with tfet and its preparation method
  • A finfet device integrated with tfet and its preparation method

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Embodiment Construction

[0034] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0035] The following is attached Figure 1-12 The present invention will be described in further detail with specific examples. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the present embodiment.

[0036] see figure 1 , figure 1 It is a schematic diagram of the three-dimensional structure of the FINFET device of this embodiment, figure 2 for along figure 1 Schematic diagram of the cross-sectional structure of the AA...

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Abstract

The present disclosure provides a FINFET device integrated with a TFET and its manufacturing method. Two end portions of the fin structure respectively form an N-type doped drain and a source which is consisted by a top P-type doped region and a bottom N-type doped region. As a result, the bottom N-type doped region of the source, the drain, the channel, the high-k dielectric layer and the gate structure on the surface of the sidewall of the fin structure form a MOS FINFET device, and the top P-type doped region of the source, the drain, the channel, the high-k dielectric layer and the gate structure on the top surface of the fin structure form the TFET device. The integration of the TFET and the FINFET is achieved, which decreases the cost.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a FINFET device integrated with TFETs and a preparation method thereof. Background technique [0002] Tunneling Field Effect Transistor (TFET) has a smaller sub-domain swing (SS, subtreshold swing), which can be lower than the semiconductor limit of 60 millivolts. Because SS is very small, the threshold voltage during switching can be very low, the switching speed can be increased, and the energy can be reduced, so it is also called a green energy-saving transistor (GFET, green FET). But the disadvantage is that the current is lower when it is turned on. A P-type heavily doped layer is formed at the source end of the FINFET structure to form a TFET connected in parallel with the double-gate MOS of the side channel, so that the current of the FINFET is dominated by the TFET in the sub-domain area, so the sub-domain area has a low swing. When turned on, it is controll...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/07H01L29/739H01L29/78H01L21/8232
CPCH01L21/8232H01L27/0705H01L29/7391H01L29/785H01L21/8221H01L21/823418H01L21/823431H01L27/0688H01L27/0886H01L29/0834H01L29/66356H01L29/66795H01L21/266
Inventor 孙德明
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT