LDPC (Low-Density Parity-Check) decoding algorithm based on variable-node lazy serial layered scheduling

A variable node, hierarchical scheduling technology, applied in the field of low-density parity-check code decoding algorithms, can solve the problems of high delay and power consumption, slow convergence, etc., to reduce delay, power consumption, and improve error The effect of code performance

Inactive Publication Date: 2017-05-31
TOEC TECH
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Problems solved by technology

However, in modern high-speed communication systems, the serial hierarchical scheduling algorithm and its

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  • LDPC (Low-Density Parity-Check) decoding algorithm based on variable-node lazy serial layered scheduling
  • LDPC (Low-Density Parity-Check) decoding algorithm based on variable-node lazy serial layered scheduling
  • LDPC (Low-Density Parity-Check) decoding algorithm based on variable-node lazy serial layered scheduling

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Embodiment Construction

[0045] LDPC code decoding algorithm among the present invention can be realized in FPGA platform, figure 2 The functional block diagram of its realization is given. The decoder includes a serial hierarchical scheduling processor (SLS processor), a lazy scheduling controller, a posteriori information (L(Q j )) and extrinsic information (L(r ij)) memory. The serial hierarchical scheduling processor (SLS processor) updates the posterior information of the variable nodes adjacent to the check node according to the posterior information and extrinsic information, and its process is consistent with the traditional serial hierarchical scheduling algorithm, and generates intermediate variables min(i) and smin(i) for the lazy scheduling controller to make decisions. The lazy scheduling controller includes a read address generator, a write address generator and a lazy judger. The lazy judger judges whether a certain variable node satisfies the lazy judgment condition according to t...

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Abstract

The invention relates to an LDPC (Low-Density Parity-Check) decoding algorithm based on variable-node lazy serial layered scheduling. A lazy serial layered scheduling algorithm based on variable-node belief degree is employed, and the algorithm is realized based on an FPGA platform. Specifically, according to the decoding algorithm, in a serial layered scheduling algorithm execution process, if the belief degree of all variable nodes adjacent to certain check function node is very reliable, the check function node is set as a lazy node and does not participate in a follow-up iterative decoding process, so the complexity of the LDPC code decoding algorithm is reduced, and the time delay and power consumption of a decoder are reduced. For the LDPC decoders in WiMAX and DVB-S2, according to the algorithm, the time delay and power consumption can be reduced by 13.9%-36.4%.

Description

technical field [0001] The present invention relates to a decoding algorithm of a low-density parity-check code (LDPC), in particular to a variable-node lazy serial layered scheduling (Variable-Node Lazy Serial Layered Scheduling, VN-LSLS) based on a factor graph LDPC decoding algorithm. Background technique [0002] In communication systems, channel coding is an effective error detection and error correction technology that reduces the impact of noise, among which Low-Density Parity-Check Code (LDPC Code) is currently the closest coding technology to Shannon's threshold . However, the complexity of the optimal algorithm for LDPC decoding and iterative equalization is too high and often cannot be realized. Therefore, it is necessary to find a suboptimal algorithm with lower complexity. The belief propagation algorithm based on the factor graph provides a decoding scheme with low complexity and good performance, among which the sum-product algorithm (SPA) is a widely used b...

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Application Information

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IPC IPC(8): H03M13/11H03M13/00
CPCH03M13/1131H03M13/114H03M13/1148H03M13/6544H03M13/6552H03M13/6555
Inventor 张建军范玉进颜凯张鹏泉
Owner TOEC TECH
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