Method and system for extracting parasitic capacitance

Abstract

The invention provides a method for extracting a parasitic capacitance. The method comprises the steps that integral circuit layout data is simulated; simulation data of integral circuit layout is acquired; and according to integral circuit technological parameters, the parasitic capacitance can be extracted from the integral circuit layout simulation data. The invention also provides a system for extracting the parasitic capacitance. According to the scheme provided by the invention, the problem that parasitic capacitance extraction is inaccurate due to geometric graph deflections of actual manufacture and integral circuit design during integral circuit manufacture can be solved effectively; and accuracy of the parasitic capacitance extraction can be increased.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to a method and system for extracting parasitic capacitance. Background technique [0002] With the development of technology, circuit optimization design has become an important stage in the integrated circuit design process. The purpose of circuit optimization is to improve the electrical performance of the circuit, and the final actual electrical performance of the circuit not only depends on the device parameter values ​​of the circuit, but also depends on the parasitic effect of the device itself, the parasitic effect between devices, the parasitic effect of the connection itself, the connection The parasitic effect between the lines, and the parasitic effect between the wiring and the device, and the parasitic effect between the adjacent wiring is particularly critical. From the perspective of circuit optimization theory, in order to obtain accurate circui...

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Problems solved by technology

[0005] The present invention provides a method and system for extracting parasitic capacitance, which solves the problem of inaccurate extraction of parasitic capacitance caused by the geometric deviation between actual manufacturing and integrated circuit design in the integrated circuit manufacturing process,

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