Memory access methods, memory controllers and processor cores

Abstract

Disclosed are a memory access method, a memory controller, and a processor core. The method comprises: receiving processor core blocking information sent by a processor core, the processor core blocking information comprising the number of remaining executable instructions of the processor core or comprising the number of the remaining executable instructions of the processor core and the number of blocking instructions of the processor core; determining a priority of each processor core according to the blocking information of each processor core; and scheduling an access request of each process core according to the priority of each processor core. The memory access method, the memory controller and the processor core in embodiments of the present invention can improve overall performance of a system.

Description

technical field [0001] The present invention relates to the field of information technology, and more specifically, to a memory access method, a memory controller and a processor core. Background technique [0002] Since the 1960s, processor performance has followed Moore's Law and continued to develop at a high speed. With the increasing integration of single-chip transistors, problems such as chip power consumption, line transmission delay, and leakage current are becoming more and more serious. It is very difficult to improve processor performance simply by increasing the main frequency. The rate of return for exploiting instruction-level parallelism is also getting lower and lower. The development of higher-level process-level parallelism and task-level parallelism has become an inevitable trend to continuously improve processor performance. The advanced architecture represented by multi-core processors has become the dominant design structure in the field of high-perfo...

AI Technical Summary

Problems solved by technology

However, the current memory access scheduling algorithms all provide bandwidth guarantees for memory access units within the same scheduling cycle, which cannot guarantee the delay of bandwidth-sensitive memory access units, and may also lead to bandwidth waste

In addition, because the on-chip memory access data flow has the characteristics of density, burst, irregularity, and unpredictability, the memory access characteristics of the application usually change with time, and the application cannot predict its own access in the next scheduling cycle. Memory characteristics, thus pre-allocating bandwidth, resulting in poor real-time performance of memory access scheduling, thus affecting the overall performance of the system

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