A level shift circuit

Abstract

The invention belongs to the technical field of integrated circuits, relates to a MOS grid drive circuit, and specifically relates to a level shifting circuit. Relative to a common level shifting circuit, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a sixth PMOS tube MP6, and a fourth NMOS tube NM4 are used for forming the level shifting circuit in the scheme provided by the invention; in combination with an auxiliary module circuit, on the one hand, the power consumption is reduced, on the other hand, the conversion speed can be accelerated, and the conversion delay is lowered.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits and relates to a MOS gate drive circuit, in particular to a level shift circuit. Background technique [0002] In some medium-speed digital-analog mixed-signal circuits and digital circuits, different modules work at different speeds. These circuits have introduced "dual drive" to ensure that some non-critical modules can work at low voltage, while the other part is analog and high-speed digital modules capable of operating at high voltages. In order to realize "dual driving", the level shifting circuit needs to be used to convert the lower logic level to a higher logic level to make the next stage module work normally. Traditional level shifting circuits (such as figure 1 As shown), there are problems that the level below the threshold cannot be converted, the conversion power consumption is large, and the propagation delay time is large. Therefore, level-shifting circuit power con...

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Problems solved by technology

[0003] The purpose of the present invention is to solve the problems of large power consumption and large propagation delay in the existing level shifting circuit, and propose a level shifting circuit

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